Modelsim warning and simulation

[Altera_Forum]

I get warning as below in gate level simulation using modelsim: 

Non-positive replication multiplier inside concat. Replication will be ignored  I have no idea what is this. Can someone give some explanation?   Besides, it is the first time i use Gate Level Simultion in modelsim. In the simulation, i found unknown state for my output signal at the beginning(0 to 6ns). Is this normal? FYI, there is no unknown state when simulate using RTL simulation.  In gate level simulation, i find out that it is much more difficult to view the internal signal as in rtl level simulation. There are too much internal signals that i am not looking for it. Is there any efficient method to get the internal signal in gate level simulation? All the internal signals wanted are in my design unit instead of altera library.  Thanks

[Altera_Forum]

Do you set the correct timescale in your testbench & provide the appropriate clock frequency during gate level simulation? 

 I think you can bring out the internal signals to I/O port so that you are able to see your desire internal signal during gate level simulation.

[Altera_Forum]

the timescale is 1ns/100ps and clk freq is 20MHz. i have uploaded the code(just a simple multiplier). Pls have a look on it. Thx