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Honored Contributor I
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Module Instantiation Problem

I have two modules in separate files sub.v and test1.v as shown below. When I attempt to compile them I get the following error messages.  

 

** Error: C:/Users/User/Documents/UCLA/Senior(2015-2016)/Summer/Verilog/Lab5/lab5.1/test1.v(7): Checker 'SUB' not found. Instantiation 's' must be of a visible checker. 

** Error: C:/Users/User/Documents/UCLA/Senior(2015-2016)/Summer/Verilog/Lab5/lab5.1/test1.v(7): A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons. 

 

Both files are in the same directory and are compiled into the same work library. I tried to add a library path that pointed to the sub module in the test1 compile settings but still got no luck. Any ideas? 

 

 

module TEST1; 

reg [31:0] a,b,c; 

 

 

initial begin 

a = 12; 

b = 9; 

SUB s(a,b,c); 

end 

 

 

endmodule 

 

 

module SUB(A, B, C); 

 

 

input [31:0] A; 

input [31:0] B; 

output [31:0] C; 

 

 

assign C = A - B; 

 

 

endmodule
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2 Replies
Highlighted
Honored Contributor I
338 Views

Hello, 

 

Instance of 'SUB' module needs to be outside initial block. Also variable c in 'TEST1' module needs to be declared as 'wire' since it is output of 'SUB' module. 

Something like, 

 

module TEST1; 

reg [31:0] a,b; 

wire [31:0] c; 

 

 

initial begin 

a = 12; 

b = 9; 

end 

 

SUB s(a,b,c); 

 

endmodule 

 

Cheers, 

Bhaumik
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Highlighted
Honored Contributor I
338 Views

Thank you for the quick reply that solved the problem! 

 

-Faraz
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