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Module parameters

Altera_Forum
Honored Contributor II
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Hi.  

 

I'm trying to create a module which has some parameters passed to it. 

This is the way I declare the module: 

 

module AAA#( 

parameter X= 11, 

parameter Y= 9 

 

 

some of the input / output wires depand on these parameters. 

 

When testing the code, I get an error: "Too many inharited module instance parameters". 

 

I do not have access to the test bench code. 

 

I would appreciate any help or comments. 

 

Thanks.
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Altera_Forum
Honored Contributor II
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A useful page to help you get to grips with passing parameters: 

http://www.asic-world.com/verilog/para_modules1.html (http://www.asic-world.com/verilog/para_modules1.html)
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