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My VHDL is a little rusty and I'm trying to get back up to speed but I've run into a problem with the code below and can't determine the source of the problem. In short, I've generated an array of registers and have reset it in two parts, registers 6 - 0 in one process and register 7 in another. This seems to not have a problem until i introduce the statement in line 51 (the bold text). The statement is to equate DATA_OUT to Fifo(0) but when not commented out causes errors: "Can't resolve multiple constant drivers for net "fifo[7][0]" I receive errors for all 9 bits in fifo[7] register. I can't see how equating the output of this register to the DATA_OUT causes multople drives in another register. Help?
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity FIFO is port( DATA_IN: in STD_LOGIC_VECTOR(8 downto 0); DATA_OUT: out STD_LOGIC_VECTOR(8 downto 0); WORD_RDY: out STD_LOGIC; FIFO_FULL: out STD_LOGIC; WORD_RD: in STD_LOGIC; WORD_WR: in STD_LOGIC; RESET_N: in STD_LOGIC; SYS_CLK: in STD_LOGIC); end FIFO; Architecture FIFOXN of FIFO is -- constant Depth: Integer:=8; type Register_Array is array(7 downto 0) of STD_LOGIC_VECTOR(8 downto 0); signal Fifo: Register_Array; signal Shift: STD_LOGIC; signal Lead_Data: STD_LOGIC_VECTOR(2 downto 0); signal Tail_Data: STD_LOGIC_VECTOR(2 downto 0); signal New_Word: STD_LOGIC_VECTOR(2 downto 0); signal Wd_Latch: STD_LOGIC; Begin -- This section defines the registers and data motion withing the -- register set. There are two pointers, Lead_Data md Tail_Data that -- track the data in the registers; Lead_Data moves the data to the -- output of the Fifo and Tail_Data moves the input data to the last -- unfilled location. data_out <= fifo(0); -- this statement causes problems. process(SYS_CLK, Fifo, Tail_Data, Lead_Data,RESET_N) variable pointer: Integer := 0; -- Note: this section runs form the same clock that is used for the X4CLOCK in the send and receive -- sections of the UART. That way there is no more than one word at an unknown location in the FIfo -- at a time. begin if RESET_N ='0' then for i in 6 downto 0 loop Fifo(i) <= "000000000"; end loop; Lead_Data <= "111"; Tail_Data <= "111"; New_Word <= "111"; elsif (SYS_CLK'event and SYS_CLK ='1') then -- Lead_Data Control Logic. This waits for the first word -- then shifts the word to the beginning of the register set -- If the last word count is "000" then the Lead_Data resets to -- "111" indicating the Fifo is empty. -- if (Lead_Data = "111") then if Wd_Latch ='1' then Lead_Data <=Lead_Data -1; end if; elsif (Lead_Data =not("000")) then Lead_Data <=Lead_Data -1; elsif (Tail_Data ="000" and WORD_RD ='1')then Lead_Data <= "111"; end if; -- This controls the Tail_Data control logic. When Lead_Data is not "111" and -- a new word is received then the Tail_Data counter shifts the new input word to -- end count +N where N is the nunber of words in the stack. N is decrumented by -- reading the head word in another section. if (Lead_Data = not("000")) then Tail_Data <=Lead_Data; elsif (Wd_Latch ='1' and WORD_RD ='0') then Tail_data <= Tail_Data +1; elsif (Wd_Latch ='1' and WORD_RD ='1') then Tail_data <= Tail_Data; elsif (Wd_Latch ='0' and WORD_RD ='0') then Tail_data <= Tail_Data -1; end if; -- This logic controls the New_Word counter. This counter tracks the new word through the -- the fifo as is is shifted to the new tail location. The Tail_Count is incrumented when -- the new word reached the back of the line. if New_Word ="111" then if Wd_Latch ='1' then New_Word <= New_word -1; pointer := pointer -1; end if; elsif New_Word =not("111") then if New_Word = Tail_Data then New_Word <= New_word - 1; pointer := pointer -1; else New_Word <= "111"; pointer := 7; end if; end if; -- This section controls the register latching operations based on the conditions of Lead_Word, -- Tail_Word, and New_Word. if Lead_Data =not("111") then for i in 7 downto 1 loop fifo(i-1) <= fifo(i); end loop; elsif New_Word = not("111") then fifo(pointer - 1) <= fifo(pointer); end if; end if; end process; -- This process controls the data entry to the lead register in the fifo array. The WORD_IN -- consists of 8 bits of data, an error bit from the receiver. process (SYS_CLK,WORD_WR, RESET_N) begin if RESET_N ='0' then Fifo(7) <="000000000"; elsif (SYS_CLK'event and SYS_CLK ='1') then if WORD_WR ='1' then Fifo(7) <= DATA_IN; Wd_Latch <='1'; else Fifo(7) <= Fifo(7); Wd_Latch <='0'; end if; end if; end process; --This is the garbage process for misc signals. process (SYS_CLK,WORD_WR, RESET_N) begin if RESET_N ='0' then FIFO_FULL <='0'; WORD_RDY <='0'; elsif (SYS_CLK'event and SYS_CLK ='1') then if Lead_Data <=X"0" then WORD_RDY <='1'; else WORD_RDY <='0'; end if; if TAIL_DATA = "111" then FIFO_FULL <='1'; else FIFO_FULL <='0'; end if; end if; end process; end FIFOXN;Link Copied
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The problem is rather caused by the below assignment which needs a constraint (e.g. if pointer <=7)
fifo(pointer - 1) <= fifo(pointer);
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Thanks. I replaced the statement with a case statement and that seemed to work. I then had second thoughts and rewrote the code to eliminate the variable use. Thanks for your help.
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