My clock port cannot be matched as a port

[Altera_Forum]

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained 

the warning message "No paths found for timing analysis". Now I'm trying with the new version Quartus II 12.1 sp1.  This is my top entity vhdl code  library ieee; use ieee.std_logic_1164.all; use work.my_types.all; entity qc_enc is generic( N: positive := 20; K: positive := 10; L: positive := 5); port( CLOCK_50: IN std_logic; KEY: IN std_logic_vector(0 downto 0); -- reset_n GPIO_0: IN std_logic_vector(K-1 downto 0); -- u GPIO_1: OUT std_logic_vector(2*L-1 downto 0));--p_ij end qc_enc;   This is the mapping on the Pin Planner window: https://www.alteraforum.com/forum/attachment.php?attachmentid=6863   I've tried to create a clock in TimeQuest Timing Analyzer with the command  create_clock -name clock -period 20.000   receiving the following errors:  Ignored filter: CLOCK_50 could not be matched with a port Ignored create_clock: Argument <targets> is an empty collection  In fact it is not present in the list of all ports:  https://www.alteraforum.com/forum/attachment.php?attachmentid=6862  Furthermore I have not any port called LVDS150p/nCEO.  Thanks in advance for your help.

[Altera_Forum]

Maybe a silly question: 

Have you successfully executed a design compilation? You need to perform at least the analysis/synthesis step in order to start timing analysis.

[Altera_Forum]

Yes, I did receiving the warning "no clock defined in the design".

[Altera_Forum]

Is CLK_50 connected in your design to an actual function? You may check the RTL netlist. 

   --- Quote Start ---  Furthermore I have not any port called LVDS150p/nCEO  --- Quote End ---   nCEO is an optional dedicated pin, I guess you have enabled it in the device settings.

[Altera_Forum]

Your Tcl syntax is wrong. 

  create_clock -name clock -period 20.000   create_clock takes a collection argument, and the [] brackets are needed to return a collection.  Cheers, Dave

[Altera_Forum]

Yes I know ... I removed the brackets because the forum gave me an error about a short tag. I fixed the post. Anyway, it seems to read only OUTPUT ports as you can see from the image in the first post.

[Altera_Forum]

Use the TimeQuest GUI directly and type commands in on the command line, eg., 

  set col query_collection -report -all $col   You can use the "Report Clocks" task to see if the constraint above correctly applied the constraint. There's nothing wrong with the syntax.  Cheers, Dave

[Altera_Forum]

set col Ignored filter: CLOCK_50 could not be matched with a port _col0

[Altera_Forum]

Excellent, that response tells you that the TimeQuest netlist doesn't see a signal named CLOCK_50. Its not a fix for your problem, but it points you to the path needed for solving it ... 

 Go and take a look at the Quartus .pin file and see what the signal names are in there.  Cheers, Dave

[Altera_Forum]

I want to let you guys help me. 

I imported the following pin assignment https://www.alteraforum.com/forum/attachment.php?attachmentid=6869 https://www.alteraforum.com/forum/attachment.php?attachmentid=6869 (most of the warnings are related to unassigned pins), and the warnings that appears are: https://www.alteraforum.com/forum/attachment.php?attachmentid=6867  https://www.alteraforum.com/forum/attachment.php?attachmentid=6868  https://www.alteraforum.com/forum/attachment.php?attachmentid=6869

[Altera_Forum]

In the file .pin there is the following row related to the pin CLOCK_50: 

CLOCK_50 : N26 : input : 3.3-V LVTTL : : 5 : N

[Altera_Forum]

Hmm, that is weird then. I would ask if you've actually used it as a clock, but your RTL view implies you are. 

 Could you post the body of your code please.  Before synthesis, its always a good idea to check the functionality of your logic using Modelsim and a testbench. If you've got a logical error that causes Quartus to determine that CLOCK_50 is not used for anything, then perhaps it is eliminating the clocked logic, and hence you no longer have a clock in your design.  And looking at your warnings file:  Warning (15610): No output dependent on input pin "CLOCK_50"  You see your problem :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I already did the testbench and it works properly, but then I slightly modified one component that was not synthesizable (a ram that loads its content from a text file).   --- Quote End ---    So what happens when you test the modified code with the testbench?   Don't post code inline. No one really wants to read it. If you want someone to look at the problem, post a zip file with the project and a synthesis Tcl script, or post a .qar file.  Cheers, Dave

[Altera_Forum]

Ok, I opened the design and synthesized it and it uses no logic cells. 

 If there are no logic cells, then no clock is required :)  Sorry, I don't have time to look at your code in detail. All I can recommend is that you synthesize each component in your hierarchy and make sure each needs logic.  One common mistake to look for is that your reset logic is inverted. However, that type of mistake would be picked up in simulation too.  Good luck!  Cheers, Dave

[Altera_Forum]

What do you mean for logic ? Registers/flip-flops ?

[Altera_Forum]

--- Quote Start ---  What do you mean for logic ? Registers/flip-flop ?  --- Quote End ---    Look at the hierarchy display in Quartus, it has a horizontal slider bar. Scroll that bar over and it tells you how many logic cells, registers, RAM blocks, DSP blocks, etc your design uses.  Use that to track down whether your parts synthesize correctly.  Cheers, Dave

[Altera_Forum]

Thank you so much for your help. I tried to compile one component at a time and the problem is the "g_ram" component. It uses 0 logic elements and I received this warning "Warning (10631): VHDL Process Statement warning at g_ram.vhd(18): inferring latch(es) for signal or variable "ram", which holds its previous value in one or more paths through the process".

[Altera_Forum]

The only way to have the component ROM compiled correctly is to use: 

subtype word_t is std_logic_vector(7 downto 0); type memory_t is array(127 downto 0) of word_t;  or  subtype word_t is std_logic_vector(7 downto 0); type memory_t is array(255 downto 0) of word_t;   In all other cases it is not able to create a memory (Memory bits = 0 and M4Ks = 0) and gives the warning "No clocks defined in design". Is this normal ?

[Altera_Forum]

The Quartus Handbook and GUI have the syntax for inferred RAM - are you using the Altera recommended procedure? 

 Personally I just use the altsyncram component, then there is no ambiguity as to what I am asking for.  Cheers, Dave

[Altera_Forum]

Yes but I think you have to use the internal memories. You cannot crete a generic size memory.

[Altera_Forum]

--- Quote Start ---  Yes but I think you have to use the internal memories. You cannot crete a generic size memory.  --- Quote End ---    You're using an FPGA, so there is no support for a generic size memory. Your inferred memory has to match what exists inside the FPGA.  Cheers, Dave