NIOSII Syntax on Quartus 13

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

NIOSII Syntax on Quartus 13

906 Views

I am having a problem verilog syntax NIOS suggest for exporting the signals into Quartus for version 13.

In some cases it suggest to use '.bidir_port_to_and_from_the_sys_scl' and in some other cases it '.sys_scl_export'. This is obviously not for the same signal.

In some cases I notice that this, what I call syntax discrepancy, is messing with the functionality of the signals.

Is this a problem? How can I fix it?

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.