Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

NativeLink - Minor Bug?

Altera_Forum
Honored Contributor II
1,140 Views

I think I found a minor bug in QuartusII/NativeLink/ModelSim. 

 

I'm using the following settings to compile and send my testbench to ModelSim: 

http://i42.tinypic.com/20pvp21.jpg  

 

However, because there are spaces in my pathing, the "script to set up simulation" fails to execute: 

http://i42.tinypic.com/4szls4.jpg  

 

The proper macro call should be enclosed in braces like so: 

do {C:/Documents and Settings/Chris Zeh/My Documents/Personal/DE0-Nano/CDC_Toggle/simulation/modelsim/wave.do

 

It seems that the \simulation\modelsim\<ProjectName>_msim_rtl_verilog.do needs a minor adjustment when it is being generated. 

 

(Or possibly I need an adjustment in where i store my files :)) 

 

Currently I'm running Quartus 32-bit Version 11.1 Build 173 11/01/2011 SJ Web Edition 

 

ModelSim ASE 10.0c, Revision 2011.09
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Altera_Forum
Honored Contributor II
396 Views

you're bound to run into more than just this problem using paths with spaces

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Altera_Forum
Honored Contributor II
396 Views

True. But it's 2012, I think we should have spaces in paths figured out by now ;)

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