Need some help on constraints for project

[Altera_Forum]

I'm using the cyclone III development board and I have the 50 MHz clock coming in and going to a PLL to give me a 200 MHz and a 65 MHz clock. The 65 Mhz clock goes to the adc where it comes back to the fpga through lvds along with 6 data channels. I have the data going through the altlvds mega function and I read in a post here, that this mega function doesn't need to be constrained.  

 So, what do I do with the clock? Should I be putting that through the altlvds function as well or is that not necessary since it's a clock? Right now I have the positive signal going to the rx_inclock of the altlvds mega function.  Also, I'm a little confused with the set clock groups command. I see in Rysc's guide that he listed the last pll output from the system_pll in a different group saying it was unrelated to the other clocks in the pll. However, its source clock is directly related to it, so why isn't that included?   This is my constraint file so far.  create_clock -period 20.000 -name clk_sys derive_pll_clocks derive_clock_uncertainty set clk_to_adc adc_Clock|altpll_component|auto_generated|pll1|clk create_generated_clock -name clk_to_adc_pin -source $clk_to_adc -offset 0.5 create_generated_clock -name clk_from_adc -source As you can see I'm not sure about the last line, the ADC_CLK is the lvds clkin signal from the adc. Also, do I need to add a set clock groups statement? There is some data transfer from the 65 MHz to the 200 MHz domain. So, as far as I can tell they all seem related. Is that a correct assumption?  I appreciate any advice or help you have. There aren't a lot of examples to go by.