Need some helping testing some VHDL Code

Altera_Forum · ‎02-19-2011

I have a project comming up, and I have some VHDL code that I really want to test.

Basically what I have so far...

Is that I created a symbol file from quartus, and this gets created with no warnings or errors or anything.

Then I create a block diagram. The dragram has 5 inputs:

CLOCK

RESETN

X[2..0] (on a bussed line of course) and

One output:

Z

Basically I want to simulate the results with the simulator tool, but I dont really understand how to created the input vectors to test this with.

Im kinda confused on how to set clock, and resetn too.

But I basically want to test my VHDL code with inputs

001, 010, 011

for several cycles.

(My VHDL is basically a statemachine, with 8 states, that loop, and does something different depending on the inputs)

Any help would be greatly appreciated, thanks!

Altera_Forum · ‎02-20-2011

You can write a VHDL testbench. and in it you can write very behavioural VHDL that you cannot synthesise. stuff like this:

signal clock : std_logic := '0';

clock <= not clock after 10 ns; -- 100 MHz clock.

reset <= '1', '0' after 25 ns;

and you can write a process like this:


process
begin
  x <= "001";
  for i in 1 to N_CLOCKS loop
    wait until rising_edge(clk);
  end loop;
  x <= "010"
  --loop again
  --etc
  wait;
end process;

Altera_Forum · ‎02-24-2011

Sorry, im very new to VHDL and quartus.

Would this code go below my current code? Or do you link them somehow?

Would creating an input vector for the simulations not be easier? or perhaps not.

Sorry for all of the silly questions. But I do appreciate the help

Altera_Forum · ‎02-24-2011

this would be in a seperate testbench file. You can create an input vector for stimulus if you want - but you would have to somehow read it into the unit under test, which is usually done in a testbench.