Need to tell Quartus to use logic and not RAM for shift registers

Altera_Forum · ‎12-14-2014

I found a couple old threads on this subject, but their solutions aren't working for me. I have a few small (12 bit by 4 or 5 cycles) pipelines in a design, and Quartus (version 13.1 at the moment) keeps dedicating RAM blocks to them.

To isolate the problem, I created this example:

module fpga_tester(
    input                                   clk,
    input                             data_in,
    output                            data_out
);
    wire  pipeline_outs ;
    pipline_helper# (.width(12), .max_delay(4)) data_pipe(.clk, .in(data_in), .out_d(pipeline_outs));
    assign data_out = pipeline_outs;
endmodule
module pipline_helper# (
    parameter                               width = 1,
                                            max_delay = 1
)(
    input                                   clk,
    input                        in,
    output  logic                out_d
);
    initial begin
        for(int n=1; n<=max_delay; n++) out_d = '0;
    end
    
    always @(posedge clk) begin
        out_d <= in;
        for(int n=2; n<= max_delay; n++) out_d <= out_d;
    end
endmodule

pipeline_helper is a module that I use in code where I need a lot of shift registers. It has multiple outputs to make it easier to reuse, but this particular code only cares about the output of the last stage.

When I build that code in Quartus, it uses a RAM block. I tried adding "//synthesis keep" to pretty much every line of it, but it still turns into RAM. I also tried going into synthesis settings and changing the maximum allowable number of RAM blocks to 0. The design still turns into RAM.

Am I missing something obvious? Are there any other constraints that would cover this?

Altera_Forum · ‎12-14-2014

http://quartushelp.altera.com/current/mergedprojects/hdl/vlog/vlog_file_dir_ram.htm

Try using:


(* ramstyle = "logic" *)    output  logic                out_d

Altera_Forum · ‎12-14-2014

Thanks, that's working great!