Negative Setup Slack time

[Altera_Forum]

Hi, 

 I am receiving a negative setup slack time .  inst|the_ddr_1|ddr_1_controller_phy_inst|ddr_1_phy_inst|ddr_1_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] of -0.706  Can anyone help with me with this and explain the reason of this? Its urgent  I have attached the file with failing paths  Sneha

[Altera_Forum]

The SOPC system is too slow. The path starts at the CPU(Nios) and ends at the DDR2 component, but I have no idea what the SOPC system looks like. There is a section in the SOPC handbook about improving performance that you might want to look at.

[Altera_Forum]

HI, 

But it will definately create a problem when I download the code in the hardware.Is it related to the specifing of the timing constraints?  Can you tell which section are you talking about?   Sneha

[Altera_Forum]

The embedded design handbook has a chapter on Avalon-MM optimizations you can take a look at. It's on the Nios II literature page and probably other places too. 

 Do you have the processor and memory interfaces on different clock domains? I suspect you have asyncronous clock crossing adapters between the CPU and SDRAM which I wouldn't recommend since those adapters only let one access through at a time. You would be better off inserting a clock crossing bridge in between or better yet operate the processor and SDRAM at the same clock frequency. Processors are very sensitive to read latency and by performing any clock crossing between the processor and memory you may hurt the performance rather than improve it.  For example if my memory operated up to 150MHz and the CPU could hit say 125MHz it would most likely be best to run them both at 125MHz. This is a generalization and it really depends on the algorithms in the code and cache topology but more often than not this would be the best optimization possible.

[Altera_Forum]

Hi, 

 I have used DDR clock timing for all the components in the sopc design to prevent the clock crossing complexity.  Do I have to put some timing constraints in the design?  I attach the sopc design image

[Altera_Forum]

Ok that looks correct. Do you have recovery or removal timing violations in the Timequest report by any chance? Also did you run the .tcl script that is generated by the SDRAM controller? Check to make sure all your I/O are constrained by going into Timequest and running the command "Show all unconstrained I/O".

[Altera_Forum]

Hi, 

 Yes I do have the time removal violation but I guess that is one of top 20 failing path and I have been able to run the code on the borad with that error of   -2.374 altera_reserved_tck pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967   But what bothers me is the setup time failure.  I think there is error in clock 1 generator from the pll in the ddr memory.The other clocks dont have any setup time issues.  I am using a ddr2 memory in EP3C120F780C7 with   speed grade of 7  pll reference clk freq 50 memory clock frequency 150 full control data rate with enabled half rate bridge   I really dont understand how to correct it.I have been looking into it for half a month now without any much progress.  Please help its very urgent to me now  I am attaching an word doc of the compilation report for the setup time.   Please give an option to attach excel sheet .It is much easy to post the errors.  I hope it can help find the problem  Sneha

[Altera_Forum]

Ah this is making more sense now. That node with the -2.374 slack is an open core plus node which is known to cause the behavior you are seeing. I'm guessing you either don't have a license for the Nios II core or the SDRAM controller. Since -2.374 is a lot of negative slack the fitter is probably trying to optimize that path to the point where it's not focusing on optimizing setup times. Try cutting that path above using wildcards and recompiling to see if your setup slack issues go away. You'll need wildcards since most of the characters in that instance name are randomized.

[Altera_Forum]

Hi, I have posted the errors before this post if you can see? 

I am using the I/O wildcards in the pin assignment editor for all the pins of the memory?  Is that what you are mentioning above? I am using the web edition 10.1sp1. It is without license

[Altera_Forum]

You should rely on the I/O constraints from the .tcl file the SDRAM controller generates and the .sdc file it generates. The path I'm talking about is the one you reported earlier: -2.374 altera_reserved_tck pzdyqx:nabboc|pzdyqx_i yatta yatta yatta That is open core plus logic that does not constrain itself. There are other forum posts about constraining this logic.

[Altera_Forum]

Hi, 

 Is is that the other setup issues are due to this warning of   altera_reserved_tck pzdyqx:nabboc|pzdyqx_  I am trying to fix it with the suggestions.

[Altera_Forum]

That's right. You can cut the output of that node so that timing analysis will not be run on those paths.

[Altera_Forum]

I am also having negative slack issues with the "altera_reserved_tck" signal going through one of the SLD nodes - I dug deep and tracked the signal down to a mega-function core called ALTDDR2 which is being used as part of the design. 

 Would give some specifics on how to "cut the output of that node" as I don't know the Altera Quartus II interface enough, yet.  Is there a way to constrain that un-constrained signal in the mega-function core or is the only solution is to "cut the output node"?  To be clear, when you "cut the output of that node", does that remove from timing analysis?  The interesting thing about this problem is that the negative slack doesn't start showing up until I have TWO SLD nodes active. If I have a single SLD node, the negative slack is no where to be found. I wonder if this issue has been investigated by Altera to be fixed?  Thanks for you help in advance!!