Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16597 Discussions

New error when programming device: "Unable to scan device chain. On-board programming hardware is disabled."

JWrig25
Beginner
3,743 Views

I have been trying to get the Avalon-MM design programmed on my Stratix V GX FPGA Development Kit. I finally got it to compile on an old version of Quartus since the newer versions are not compatible with the design. I have tried to then program my board with the design but I run into the error above. I have been able to program the board successfully in the past and have no idea why it stopped working now. I made sure all the DIP switches are in the correct factory default positions but that did not fix the issue. I am on my second FPGA board since the first one stopped working like my second just stopped and also gave me the same error. Everything suggested to me to fix it requires that I can program with the board in Quartus or can connect to the BTS or BUP which I cannot do. The BTS gives me the error: "Connecting to the target... java.lang.Exception: No USB Blaster detected. Please check connections and restart the program". When I try to program on Quartus, it will recognize the USB_Blaster II but gives me the error "Unable to scan device chain. On-board programming hardware is disabled". Please help, I have had nothing but problems with these FPGA boards, with Quartus not programming, designs specific to my FPGA not compiling, other issues and now this.

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24 Replies
JWrig25
Beginner
599 Views

How would I go about removing that device?

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JohnT_Intel
Employee
599 Views

Hi,

 

I know that this is hard but I suspect that the issue is due to this device which cause JTAG chain is broken.

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JohnT_Intel
Employee
599 Views

Hi,

 

If you are not able to remove it then I couldn't figure out a way to debug the issue on the JTAG Chain

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JGlez1996
Employee
572 Views

hello Jwrig25, I had the same problem, lets try with the configuration of dip switches for the Board Test System in the FPGA User Guide

 

cheers

Jose G.

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