Nios Simulation Outside of SOPC

[Altera_Forum]

Hi,  

 I have been following the Simulating Nios II Embedded Processor Design (http://www.altera.com/literature/an/an351.pdf) tutorial to simulate a Nios Processor Embedded System. By following the guide, I found out that it uses SOPC to generate ModelSim execution scripts. However, for my project, after the SOPC generates 4 separate systems (each with their own nios processor, memory, dma, router, etc), I still need to connect the 4 separate routers together in another top-level design file instantiating the nios_system generated by SOPC. Therefore, I was wondering, is the ModelSim simulation based solely on the outputs of SOPC (in which case it might not be aware of connection established in the top-level design file later), or perhaps there is a way to link ModelSim to simulate the top-level file, instead of just the SOPC outputs?  Please let me know.  Thanks.

[Altera_Forum]

hi lc2454, 

 No problem. Write your own testbetnch, copy DUTs from sopc-generated files and simulate by own scripts. Give only different names ram-init files for each processor.

[Altera_Forum]

Hi,  

 Thank you for your reply. Writing my own scripts is definitely something I can do for the components that I have coded in VHDL, but I am not sure how I would simulate the nios2 processor, dma, on-chip memory, or basically just components provided by Altera. Do you think you can elaborate on how to do that or provide me with resources that help me do that?  Thanks.

[Altera_Forum]

You should compile only one file for whole system. For exampe, if you've named it my_nios, compile only my_nios.vhd and add +include option with path to quartus dir to vcom command. look at the my_nios file carefully and you can see at the and mini-testbench with DUT instatnce. You can use it as template for you own tb.

[Altera_Forum]

Thanks for your reply.  

 I understand what you are saying. However, the testbench provided at the end of "nios_system" (that's what I call it) is small and doesn't provide much insight to how to simulate the nios 2 processor and other Altera provided components. I guess I will try to figure this out by looking at other resources. If you know of any tutorial or links, please let me know.

[Altera_Forum]

--- Quote Start ---  Thanks for your reply.    I understand what you are saying. However, the testbench provided at the end of "nios_system" (that's what I call it) is small and doesn't provide much insight to how to simulate the nios 2 processor and other Altera provided components. I guess I will try to figure this out by looking at other resources. If you know of any tutorial or links, please let me know.  --- Quote End ---     You can edit the testbench and compile the file. I usually add my own testbench code in the testbench portion. If you look at the file properly, you will see that there is a space provided in the simulation file for user's own code. There is space for both: writing a top-level entity and its test bench. Good thing is when you regenerate the simulation file in SOPC system, the user code (written in the user code space mentioned above) remains intact. The same is though not true if the user changes the "scripts"; when the simulation scripts are generated they wipe out any modifications done by the user.