- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I have a question about simulating nios embedded systems with ModelSim. I have been following the guide Simulating Nios II Embedded Processor Design (http://www.altera.com/literature/an/an351.pdf) for my own project and run into some unexpected problems. I tried to run a C program that writes some data through the Avalon Bus to a VHDL-coded router and network interface. The error log from ModelSim is as follows:run 800us# NIOS Core 3# Start Receive...# 0# 264410 ns: WARNING: cpu_4_test_bench/av_ld_data_aligned_unfiltered is 'x'# 264930 ns: ERROR: cpu_4_test_bench/W_wr_data is 'x'# ** Failure: VHDL STOP# Time: 264930 ns Iteration: 1 Process: /test_bench/dut/the_cpu_4/the_cpu_4_test_bench/line__550 File: /home/lc2454/Documents/6847/nocDMA/cpu_4_test_bench.vhd# Break at /home/lc2454/Documents/6847/nocDMA/cpu_4_test_bench.vhd line 562
The piece of VHDL code throwing the error is as follows: process (clk, reset_n)
VARIABLE write_line5 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(W_wr_data) then
write(write_line5, now);
write(write_line5, string'(": "));
write(write_line5, string'("ERROR: cpu_4_test_bench/W_wr_data is 'x'"));
write(output, write_line5.all & CR);
deallocate (write_line5);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
It looks like it's complaining about some data written but I find it difficult to debug the issue because it doesn't show any printf statements for the code it runs. For example, it seems like the error is coming from cpu_4, but there are no evidence of any debug statements shown for that cpu. Therefore, I was wondering if any1 has run into similar scenarios or have ideas on how to resolve this issue. Please let me know. UPDATE: After debugging around for a bit, it seems like the error stems from this piece of C code. int getReady(int base)
{
return IORD_32DIRECT(base, 64*4);
}
which is a function I wrote to read data from the Avalon Bus to poll the status bit of the network interface after it has finished transferring data. However, I don't know what's wrong with this from a simulations standpoint. Thanks.
Link Copied
0 Replies

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page