No PLL output on modelsim

[Altera_Forum]

Hi all,  

I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it with 50MHz clock and i see no output on both the output signals. Please see the files below for .bdf and modelsim screenshot. Please help me how to see the output and what changes i need to make.   Thank you Ash

[Altera_Forum]

do you think the input-clock is 50MHz?

[Altera_Forum]

Hi Ash, 

 Just to check with you if the pll_locked got asserted? Can you try to apply a reset to the PLL?

[Altera_Forum]

yea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock

[Altera_Forum]

Hi akira, 

yea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock Thanks

[Altera_Forum]

Hi tiny007,  

I added a reset as per what you said. still the output remains the same Undefined. Is there somewhere i am going wrong?

[Altera_Forum]

Hi amod, 

 Two things: you only show 5-6 ns on your waveforms, the PLL models, like real PLLs, take some time to initialize and sync before you get an output. 6ns is not nearly enough time. I forget how long this takes in simulation (I think it's a lot less than for the real devices) but give it a us or so before you give up. Second, it looks like the clock you're feeding it is NOT 50MHz, but 10GHz! The period shown is 0.1ns, check your clock generation.  -Fred

[Altera_Forum]

FredH is right. Where is your testbench? Post it here.

[Altera_Forum]

Hi FredH i have changed the clock period to 0.02 us and run the simulation for half a second. still my output remains the same. Please see the attachment.  

Thanks  Ash

[Altera_Forum]

Hi krasner,  

  Could you please explain me how to generate testbench ?

[Altera_Forum]

Are you getting any warning when you run modelsim? Perhaps a library is not set up. See this thread: http://www.alteraforum.com/forum/showthread.php?t=21634

[Altera_Forum]

A testbench is simply a verilog or vhdl script where you set up you input signals to the system that you are simulating. Usually, you would write one by hand. 

 How did you set up the input clock signal to your pll system?

[Altera_Forum]

yea there is and its Warning: (vsim-3473) Component instance "b2v_inst : altpll0" is not bound.

[Altera_Forum]

ok my input clock signal is the input pin clk1 in the bdf file 50MHz. if i look into ppl1.vhd file. i dont have altera_mf header file. Can this be the problem ?

[Altera_Forum]

OK this means you are missing the pll library. Make sure you are including all the altera libraries in your modelsim environment.

[Altera_Forum]

ok i found out that. Is there a way do that ? Can you direct me here please? I need to get this work.

[Altera_Forum]

Yup. you have to include the altera_mf library

[Altera_Forum]

It should me under C:/altera/modelsim_ase/altera/<vhdl or verilog>/altera_mf 

 You have to provide that path

[Altera_Forum]

This is a screenshot of the library panel in the modelsim. This contains altera_mf library. But in the vhdl file i dont have altera_mf libary. Please see the screenshots.

[Altera_Forum]

posting the attachments again.

[Altera_Forum]

In your vhdl file try including LIBRARY altera_mf; 

USE altera_mf.all;