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Using simple logic circuit, simulating using University Program VWF. Changed simulation options from 'win32aloem' to 'questa.fse/win64'. Deleted '-no vopt' Everything complies and does functional simulation, but no output function timing diagram.
Problem only occurred when updating intelFPGA_lite v20.1 to 22.1 std
Thanks
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I found the solution searching other posts.
Simulation Options, edit the 'vsim' line.
remove '-novopt' and replace with '-voptargs=+acc'
The output timing diagram displays properly.
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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