No output in simulation for Division implemented using IP Core

[Altera_Forum]

hello everyone, I have design the division module with the help of lpm_divide. I am using Quartus Prime Lite Edition. I have done simulation on ModelSim Altera Starter Edition. i am getting only High Impedence at the output. What can be the problem?

[Altera_Forum]

Could you provide more detailed information: have you forced any values, cause modeling start with 'U' value in simualtion, you don't have 'z' i assume.

[Altera_Forum]

Is your clock running?

[Altera_Forum]

--- Quote Start ---  Could you provide more detailed information: have you forced any values, cause modeling start with 'U' value in simualtion, you don't have 'z' i assume.  --- Quote End ---    If it is Verilog, then the value may be 'Z' as there is no 'U'