Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Partial Reconfiguration : sld_hub instance creates compilation issue

Altera_Forum
Honored Contributor II
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I am compiling for design which requires Partial Reconfiguration. I got this error while compiling 

 

Error (142045): Detected unsupported compiler-generated partition "sld_hub:auto_hub" in a project with partial reconfiguration enabled. 

 

My design comprises of a qsys block with PCIe and Memory Controller and nothing else. There is no NIOS and I am not enabling signaltap (unchecked the box Enable Signatap II Logic Analyzer in settings). 

 

Any idea how I could remove sld_hub from my design which is auto generated during compilation?
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Altera_Forum
Honored Contributor II
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Hi, 

I guess you have already found the solution, but, one possible solution can be like this. Or at least for me, i see it solves the problem. 

 

You define partitions for your design.  

Also you define logic lock regions. And you assign your partitions to logic lock regions and define the region to be partial re-configurable.  

 

Now, if you forget to allow multiple personas for the partial block, you will encounter that error. (i am talking about quartus prime)  

 

So simply right click on your partition, and enable Allow multiple personas field.  

 

MO
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