Not working; Previously created .QSYS file in a new project.

[Altera_Forum]

Hello everyone, 

 I'm trying to use a previously created .QSYS file in a new project. But, when I try to run the "Memory Test" SW application from Eclipse, it's not working and it gives an error message. Here are the steps that I'm using:     1. I created a new Quartus II project   2. I took the .qsys file (The .qsys file was created in another project, using the SOPC to QSYS migration tool.), and added it to the new project directory. (The .qsys file was working properly in the project it was created in).   3. I changed the name of the <filename>.qsys file to something else, <new_filename>.qsys and I generate the QSYS design.   4. At the toplevel I instantiate the QSYS design, and for the .QSF file I add the constraints. Then I compile the Quartus II project successfully.    5. I go to Eclipse and create the "Memory Test" SW application.   6. I download the .SOF to the FPGA   In the Eclipse "Run Configuration" window, Eclipse is saying that there is a mismatch for the "system id" and for the "system timestamp" (I was not getting this in the original (old) project). I proceed by checking the "System ID checks" under Target Connection.   When I try to run the "Memory Test application, I'm not able to. I'm getting an error message saying: "Downloading ELF Process failed".     So, why can't I use the <new_filename>.qsys in the new project??   There is'nt much difference between the old and the new project, only some name changes. For .SOPC files I have previously made this sort of name change, and it has been successfull.   Saber890

[Altera_Forum]

In Eclipse when you create the new application, did you create a new BSP too? Does this new BSP use the new .sopcinfo file and not the old one?

[Altera_Forum]

I make sure to create a new .BSP in Eclipse everytime I generate a new .sopcinfo file.  

 I delete the old .BSP, and go to File -> New -> Nios II Board Support Package and provide the path to the .sopcinfo file inorder to create a new .BSP.    I make sure the FPGA is configured with the correct .SOF file.   Also, pressing the "Refresh Connections" button (for the JTAG_UART connection) under the "Target Connection" is not helping inorder to remove the System ID/timestamp mismatches.   When trying to run the SW application, the console window displays:   "Pausing target processor: not responding.  Resetting and trying again: FAILED",    before the "Downloading ELF Process failed" message pops up.        saber890

[Altera_Forum]

You should first solve the system ID problem. As long as this isn't fixed you shouldn't try to run the application. 

Each time you re-generate the QSys sytem, new system ID and timestamp values are written in two places: in the generated HDL files, that are later compiled by Quartus, and in the .sopc info file that is read by Eclipse to generate the BSP. If you have a system ID problem here, it means that you have an inconstitency between what Eclipse thinks it should read, and what is actually returned by the FPGA. It can be either because Eclipse is using an older version of the .sopc info file, because Quartus compiled the .sof file with an old version of the generated QSys system, or because the .sof image currently in the FPGA isn't the latest one. I also had license problems several times, and then Quartus generated the image in a different file, a _time_limited.sof. As I was still uploading the other .sof file into the FPGA I had an inconsistency. Can Eclipse show you the expected timestamp and the actually read value? That way you could at least show which one is the more recent.

[Altera_Forum]

The system id/timestamp seems a bit inconsistent. Even if the same .sopcinfo is used when creating the .SOF file and also for creating the .BSP in Eclipse, the mismatch sometimes appear. Not sure if this is caused by some fault in the HW that I'm working on, but it's clearly confusing Eclipse.  

 Anyhow, I once again followed the initial procedure, (creating a new Quartus II project, added the <filename>.qsys file, renamed it..etc), and this time it worked(no system id/timestamp mismatch and the memory test is running for successfully for both the Flash and the SRAM devices).    I Might have overlooked something, thank you for taking the time to reply.     Saber890 

[Altera_Forum]

hi again,  

 just thought I mention another thing which in my case is causing System ID/timestamp mismatch, and also failure to even start running the Eclipse SW application (giving the "Downloading ELF Process failed" error message).   I have a .SDC constraints file in the project, with just a couple of lines:   create_clock -period 20.0 -name clkin_50 [get_ports {clkin_50}] derive_pll_clocks -create_base_clocks derive_clock_uncertainty     If the .SDC file is not included the project, the "Memory Test" fails to even start.   (This is for the SOPC design which is being migrated to QSYS. So this is probably why the QSYS design was failing as well).     Saber890