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Altera_Forum
Honored Contributor I
858 Views

Odd behavior with matching-case (vhdl 2008)

Hello! 

I'm trying to use the matching-case syntax introduced in vhdl 2008 but I'm having a bit of a problem. Take the following piece of code, say a register map for example: 

clk : in std_logic; rst : in std_logic; addr : in std_logic_vector(7 downto 0); reg0 : out std_logic; reg1 : out std_logic; reg2 : out std_logic; reg3 : out std_logic .... process (rst, clk) begin if (rst = '1') then reg0 <= '0'; reg1 <= '0'; reg2 <= '0'; reg3 <= '0'; elsif (rising_edge(clk)) then reg0 <= '0'; reg1 <= '0'; reg2 <= '0'; reg3 <= '0'; case? addr is when x"00" => reg0 <= '1'; when x"1-" => if (addr(3 downto 0) = "0011") then reg1 <= '1'; else reg2 <= '1'; end if; when others => reg3 <= '1'; end case?; end if; end process; 

 

The second when in the case above is where I'm having trouble. The compiler will set reg1 to always '0' (which you can check in the RTL viewer). This sort of makes sense to me because since you told the compiler you didn't care about the first 4 bits it just assumed the if would fail and reg1 is hardwired to '0'. However, I'm not entirely convinced this assumption is correct, what I would expect is to always fall into this specific case regardless of the lower 4bits but sill use their actual value inside. For example, if you changed it to when x"1-" => dataout <= addr(3 downto 0) wouldn't you expect the output to be the same as the 4 lower bits of the address input? Compiling this gives you a dataout stuck at GND (as notified by a warning message or seen in the RTL viewer). 

 

Thank you all for your help!
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3 Replies
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Hello! 

I'm trying to use the matching-case syntax introduced in vhdl 2008 but I'm having a bit of a problem. Take the following piece of code, say a register map for example: 

clk : in std_logic; rst : in std_logic; addr : in std_logic_vector(7 downto 0); reg0 : out std_logic; reg1 : out std_logic; reg2 : out std_logic; reg3 : out std_logic .... process (rst, clk) begin if (rst = '1') then reg0 <= '0'; reg1 <= '0'; reg2 <= '0'; reg3 <= '0'; elsif (rising_edge(clk)) then reg0 <= '0'; reg1 <= '0'; reg2 <= '0'; reg3 <= '0'; case? addr is when x"00" => reg0 <= '1'; when x"1-" => if (addr(3 downto 0) = "0011") then reg1 <= '1'; else reg2 <= '1'; end if; when others => reg3 <= '1'; end case?; end if; end process; 

 

The second when in the case above is where I'm having trouble. The compiler will set reg1 to always '0' (which you can check in the RTL viewer). This sort of makes sense to me because since you told the compiler you didn't care about the first 4 bits it just assumed the if would fail and reg1 is hardwired to '0'. However, I'm not entirely convinced this assumption is correct, what I would expect is to always fall into this specific case regardless of the lower 4bits but sill use their actual value inside. For example, if you changed it to when x"1-" => dataout <= addr(3 downto 0) wouldn't you expect the output to be the same as the 4 lower bits of the address input? Compiling this gives you a dataout stuck at GND (as notified by a warning message or seen in the RTL viewer). 

 

Thank you all for your help! 

--- Quote End ---  

 

 

May be the tool is saying you made up your mind that you don't care about lower 4 bits then you contradicted that....
Altera_Forum
Honored Contributor I
33 Views

I would raise this as a synth bug to altera, as you will now have a simulation/synthesis missmatch. 

Any chance you have a Prime pro license? Prime pro is meant to have full vhdl 2008 support, so I assume a different compile engine.
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

I would raise this as a synth bug to altera, as you will now have a simulation/synthesis missmatch. 

Any chance you have a Prime pro license? Prime pro is meant to have full vhdl 2008 support, so I assume a different compile engine. 

--- Quote End ---  

 

 

You're right, it was such a simple usecase I didn't even bother simulating it (I did test the feature in modelsim a while ago, but this is the first time we're actually using it in project outside just simulation). If you simulate my example above (out <= addr(3 downto 0)) it does behave like I expected it to, but the compilation results are different. 

Unfortunately I only have Prime web edition. We do have a license for Quartus 12 but that's so old right now I'm not sure if it's even useful testing it there. 

 

I will raise this bug to Altera as soon as I get back to work on Monday. Thank you for your input!
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