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Honored Contributor I
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Verilog coding help

Hi 

 

I have a ep4ce6 fpga board and I am trying to make a counter that counts up to 2_999_999_999.I don't know why it's not working. Here is the code: (I am trying to make a 1 sec timer) What am I doing wrong. I am selecting a verilog file in 

the Quartus Application. The code compiles but led does not light up every second. 

 

module mycounter 

input clk, //50MHz onboard clock PIN 23 

input reset, 

 

output led 

); 

 

reg [25:0] counter; //26 bit - count up to 50_000_000 to generate 1 sec  

reg tmp; 

 

//COUNT 

always @(posedge clk) 

if(~reset) 

counter <=0; 

else 

counter <= counter + 1; 

 

//COUNT Comparator 

always @(*) tmp = (counter == 26'd49_999_999);// 

 

assign led = tmp;//I want the led to light up every second - IT DOESN'T ??? 

 

 

endmodule 

 

Thanks 

 

Saleem
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11 Replies
Highlighted
Honored Contributor I
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--- Quote Start ---  

Hi 

 

I have a ep4ce6 fpga board and I am trying to make a counter that counts up to 2_999_999_999.I don't know why it's not working. Here is the code: (I am trying to make a 1 sec timer) What am I doing wrong. I am selecting a verilog file in 

the Quartus Application. The code compiles but led does not light up every second. 

 

module mycounter 

input clk, //50MHz onboard clock PIN 23 

input reset, 

 

output led 

); 

 

reg [25:0] counter; //26 bit - count up to 50_000_000 to generate 1 sec  

reg tmp; 

 

//COUNT 

always @(posedge clk) 

if(~reset) 

counter <=0; 

else 

counter <= counter + 1; 

 

//COUNT Comparator 

always @(*) tmp = (counter == 26'd49_999_999);// 

 

assign led = tmp;//I want the led to light up every second - IT DOESN'T ??? 

 

 

endmodule 

 

Thanks 

 

Saleem 

--- Quote End ---  

 

 

If your led is lit for just 1 clock period of 20 ns you won't see it.
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Honored Contributor I
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@saleem, 

 

You might find this article about handling timing within an fpga (http://zipcpu.com/blog/2017/06/02/generating-timing.html), or here regarding how to do debugging with an led (http://zipcpu.com/blog/2017/05/24/serial-port.html). Both will discuss some of the issues you are having. 

 

As a very first design for a board, I also once used this design to determine the clock speed (http://zipcpu.com/blog/2017/05/19/blinky.html) of the incoming clock to a board I had (100MHz--although the schematic had said 25MHz). 

 

Hope these help, 

 

Dan
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Highlighted
Honored Contributor I
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--- Quote Start ---  

@saleem, 

 

You might find this article about handling timing within an fpga (http://zipcpu.com/blog/2017/06/02/generating-timing.html), or here regarding how to do debugging with an led (http://zipcpu.com/blog/2017/05/24/serial-port.html). Both will discuss some of the issues you are having. 

 

As a very first design for a board, I also once used this design to determine the clock speed (http://zipcpu.com/blog/2017/05/19/blinky.html) of the incoming clock to a board I had (100MHz--although the schematic had said 25MHz). 

 

Hope these help, 

 

Dan 

--- Quote End ---  

 

 

Dividing clock is not a good advice I am afraid. Dividing using clock enable is the recommended practice. 

The counter of OP is neither constrained and so is not pulsing every 50MHz nor a single pulse will be visible on led.
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Honored Contributor I
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--- Quote Start ---  

If your led is lit for just 1 clock period of 20 ns you won't see it. 

--- Quote End ---  

 

 

Absolutely correct. Try something like this instead: 

 

assign led = counter[25]; or 24 or 23 or ... to make the led blink faster and faster 

 

and lose the usage of the tmp register entirely.
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Honored Contributor I
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@kaz, 

I'm not sure which of the three posts you are referring to, or which section within them, but I've tried to be consistent with your observation throughout the entire blog. If not, please quote the location in the article where I made that mistake so I can fix it. 

Thanks, 

Dan
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Highlighted
Honored Contributor I
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--- Quote Start ---  

@kaz, 

I'm not sure which of the three posts you are referring to, or which section within them, but I've tried to be consistent with your observation throughout the entire blog. If not, please quote the location in the article where I made that mistake so I can fix it. 

Thanks, 

Dan 

--- Quote End ---  

 

 

I am referring to your first link you posted that discusses clock division under the title "handling timing".
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Honored Contributor I
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@kaz, 

So ... you would recommend I place a comment prior to the "Strobe Signal" section recommending that users not use a "divided" clock to drive their logic? 

Dan
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Honored Contributor I
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--- Quote Start ---  

@kaz, 

So ... you would recommend I place a comment prior to the "Strobe Signal" section recommending that users not use a "divided" clock to drive their logic? 

Dan 

--- Quote End ---  

 

 

For internal fpga logic running at conventional speeds yes do not divide clock to use it as clock as it leads to various hold problems and could upset Rysc. Keep the fast clock and use divided output as clk enable. 

For LED control it does not matter at all as LEDs need very slow drive and this is not the main theme for fpga design though it is attractive for tutors and students projects. 

 

Moreover the title of the link is confusing as we normally mean by "timing" the register timing (setup and hold as checked by timing tool). It should be titled "clocking...something"
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Honored Contributor I
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@kaz, 

 

Would a comment, such as the following, be sufficient to address your concerns? 

 

As a first rule, do not drive your logic like this: 

always @(posedge counter)     begin         // DON'T DO THIS     end  

This will cause you all kinds of grief, either leading you to an unreliable design, or forcing you to deal with multiple clock domains, clock domain transfers, and worse. Unless you really know what you are doing … don’t use this approach. 

 

As for the word "timing", I'm kind of stuck. It does have the specific idiomatic meaning within the context of FPGA's that you state above, but it also has the traditional english meaning (https://www.google.com/search?client=ubuntu&channel=fs&q=timing&ie=utf-8&oe=utf-8) of: 

 

the choice, judgment, or control of when something should be done. 

"one of the secrets of golf is good timing" 

 

a particular point or period of time when something happens. 

plural noun: timings 

 

 

It was this latter meaning I was intending to use. Is there any particular synonymn that you think would be better? "Controlling Sequencing" for example? 

 

Dan
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Honored Contributor I
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--- Quote Start ---  

@kaz, 

 

Would a comment, such as the following, be sufficient to address your concerns? 

As a first rule, do not drive your logic like this: 

always @(posedge counter) begin // DON'T DO THIS end  

This will cause you all kinds of grief, either leading you to an unreliable design, or forcing you to deal with multiple clock domains, clock domain transfers, and worse. Unless you really know what you are doing … don’t use this approach. 

 

As for the word "timing", I'm kind of stuck. It does have the specific idiomatic meaning within the context of FPGA's that you state above, but it also has the traditional english meaning (https://www.google.com/search?client=ubuntu&channel=fs&q=timing&ie=utf-8&oe=utf-8) of: 

the choice, judgment, or control of when something should be done. 

"one of the secrets of golf is good timing" 

 

a particular point or period of time when something happens. 

plural noun: timings 

 

 

It was this latter meaning I was intending to use. Is there any particular synonymn that you think would be better? "Controlling Sequencing" for example? 

 

Dan 

--- Quote End ---  

 

 

I don't want to pretend I am as good in English as our chief moderator Tricky but I suggest tilte to be "How to Divide clock and how to use the divided clock" 

 

Yes keep clock edge statement clean of any divided clock but follow it by divided clock: 

 

always @(posedge clean_clock) begin if divide_clk then //dirty divided clk ... end end
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Honored Contributor I
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Thank you all for your help and suggestions. 

 

Saleem
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