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Altera_Forum
Honored Contributor I
2,788 Views

Easiest Testbench for my VHDL code (multiplication)

Hello there. Is there somebody who can make testbench from my vhdl code? It is multiplication of 2 integers, which are n-1 downto 0.. n=16. Thanks a lot..  

library IEEE;use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity MultExample is Generic ( n : natural := 16); Port (A,B : in std_logic_vector(n-1 downto 0); Q : out std_logic_vector(n*2-1 downto 0); end MultExample; architecture Behavioral of MultExample is BEGIN Q <= std_logic_vector(signed(A) * signed(B)); end architecture Behavioral;
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Altera_Forum
Honored Contributor I
664 Views

Thanks a lot for these files.. But i don't know what to write to UUT.. It is empty and i need to put values there.

Altera_Forum
Honored Contributor I
664 Views

 

--- Quote Start ---  

Thanks a lot for these files.. But i don't know what to write to UUT.. It is empty and i need to put values there. 

--- Quote End ---  

 

 

option 1: don't write any testbench. Just use mult module with inputs initialised to values of your choice and check output on waveform. 

option 2: write testbench as counting sequences to drive the inputs. 

option 3: don't do anything and trust the mult as we do. once your project is mature you can testbench your whole project
Altera_Forum
Honored Contributor I
664 Views

I need testbench.. It is school homework but i don't know how to edit it.

Altera_Forum
Honored Contributor I
664 Views

Hi 

 

Have you tried option 1??  

Learn to write test-bench google it. 

http://eng.umb.edu/~cuckov/classes/engin341/lectures/l02%20-%20vhdl%20-%20dataflow%20and%20structura... 

--ONE OF THE WAY OF WRITING TB IS SHOWN YOU CAN USE LOOPS TO TEST ALL THE CASE stimulus: process begin a<="0101"; b<="0101"; wait for 20ns; a<="1111"; b<="1111"; wait; end process;  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
664 Views

 

--- Quote Start ---  

Hi 

 

Have you tried option 1??  

Learn to write test-bench google it. 

http://eng.umb.edu/~cuckov/classes/engin341/lectures/l02%20-%20vhdl%20-%20dataflow%20and%20structura... 

--ONE OF THE WAY OF WRITING TB IS SHOWN YOU CAN USE LOOPS TO TEST ALL THE CASE stimulus: process begin a<="0101"; b<="0101"; wait for 20ns; a<="1111"; b<="1111"; wait; end process;  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

Hello, i have tried with Q too or i dont need to? I got errors: 

# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(96): near "'": syntax error# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(97): near "'": syntax error# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(98): near "'": syntax error# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(100): near "'": syntax error# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(104): VHDL Compiler exiting# ** Error: D:/altera/13.0sp1/modelsim_ase/win32aloem/vcom failed. 

This is my code for test bench:  

library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_Std.all; entity nasobenie_tb is generic ( DATA_WIDTH : natural := 4 ); end; architecture bench of nasobenie_tb is component nasobenie generic ( DATA_WIDTH : natural := 4 ); port ( a : in signed ((DATA_WIDTH-1) downto 0); b : in signed ((DATA_WIDTH-1) downto 0); q : out signed ((2*DATA_WIDTH-1) downto 0) ); end component; signal a: signed ((DATA_WIDTH-1) downto 0); signal b: signed ((DATA_WIDTH-1) downto 0); signal q: signed ((2*DATA_WIDTH-1) downto 0) ; begin -- Vlozenie hodnot pre parameter generic !! uut: nasobenie generic map ( DATA_WIDTH => DATA_WIDTH ) port map ( a => a, b => b, q => q ); stimulus: process begin a <= '0000'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0001'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0010'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0011'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0100'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0101'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0110'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '0111'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1000'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1001'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1010'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1011'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1100'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1101'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); a <= '1111'; b <= '0000'; wait for 10 ns; assert(q = '00000000'); end process; --koniec opisu procesov end bench; --koniec opisu architektury tb configuration cfg_bench of nasobenie_tb is --konfiguracia test bench entity for bench --cyklus je prazdny, nema ziadnu specificku funkciu v nasom pripade end for; --koniec cyklu end cfg_bench; --koniec opisu konfiguracie
Altera_Forum
Honored Contributor I
664 Views

for strings (like arrays) you should be using double quotes, not single quotes. 

Also, with your asserts, you are not reporting, so I doubt you will get a meaningful message.
Altera_Forum
Honored Contributor I
664 Views

Thanks for help. One more problem: 

# ** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 2 (3 downto 2). # Time: 0 ps Iteration: 0 Process: /nasobenie_tb/stimulus File: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd # Fatal error in Process stimulus at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd line 41 # # HDL call sequence: # Stopped at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd 41 Process stimulus #  

I don't know how to fix that.. I am using 4 downto 2 is it bad? I have 2 bits and after multiplication i got 4 bits or I am wrong? Thanks.
Altera_Forum
Honored Contributor I
664 Views

I think the error is fairly self explanitory. 

wherever the error is, the widths do not match. The left side requires 4 bits, but you're only assigning 2
Altera_Forum
Honored Contributor I
664 Views

It is multiplication.. When i multiply 2 bits and 2 bits number, result is 4 bits or i am wrong?  

How to solve it? Any solution? Can you tell me which one change and to what value..
Altera_Forum
Honored Contributor I
664 Views

Yes, multiplying 2 bit numbers gives a 4 bit result. 

The error you posted is not in the code you posted, so I have no idea how to fix it.
Altera_Forum
Honored Contributor I
664 Views

I will try to send there both codes.. 

nasobenie.VHD:  

-- Quartus Prime VHDL Template -- Signed Multiply library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nasobenie is generic ( DATA_WIDTH : natural := 8 ); port ( a : in signed ((DATA_WIDTH-1) downto 0); b : in signed ((DATA_WIDTH-1) downto 0); q : out signed ((2*DATA_WIDTH-1) downto 0) ); end entity; architecture rtl of nasobenie is begin q <= a * b; end rtl;  

 

And now nasobenie_tb.vhd 

library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_Std.all; entity nasobenie_tb is generic ( DATA_WIDTH : natural := 4 ); end; architecture bench of nasobenie_tb is component nasobenie generic ( DATA_WIDTH : natural := 2 ); port ( a : in signed ((DATA_WIDTH-1) downto 0); b : in signed ((DATA_WIDTH-1) downto 0); q : out signed ((2*DATA_WIDTH-1) downto 0) ); end component; signal a: signed ((DATA_WIDTH-1) downto 0); signal b: signed ((DATA_WIDTH-1) downto 0); signal q: signed ((2*DATA_WIDTH-1) downto 0) ; begin -- Vlozenie hodnot pre parameter generic !! uut: nasobenie generic map ( DATA_WIDTH => DATA_WIDTH ) port map ( a => a, b => b, q => q ); stimulus: process begin a <= "00"; b <= "00"; wait for 10 ns; a <= "00"; b <= "01"; wait for 10 ns; a <= "00"; b <= "10"; wait for 10 ns; a <= "00"; b <= "11"; wait for 10 ns; a <= "01"; b <= "00"; wait for 10 ns; a <= "01"; b <= "01"; wait for 10 ns; a <= "01"; b <= "10"; wait for 10 ns; a <= "01"; b <= "11"; wait for 10 ns; a <= "10"; b <= "00"; wait for 10 ns; a <= "10"; b <= "01"; wait for 10 ns; a <= "10"; b <= "10"; wait for 10 ns; a <= "10"; b <= "11"; wait for 10 ns; a <= "11"; b <= "00"; wait for 10 ns; a <= "11"; b <= "01"; wait for 10 ns; a <= "11"; b <= "10"; wait for 10 ns; a <= "11"; b <= "11"; wait for 10 ns; end process; --koniec opisu procesov end bench; --koniec opisu architektury tb configuration cfg_bench of nasobenie_tb is --konfiguracia test bench entity for bench --cyklus je prazdny, nema ziadnu specificku funkciu v nasom pripade end for; --koniec cyklu end cfg_bench; --koniec opisu konfiguracie
Altera_Forum
Honored Contributor I
664 Views

The error you have posted doesnt appear to be for this code. 

I suggest deleting the configuration from the code.
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