On chip RAM not recognized by NIOS CPU connected through custom bridge

[Altera_Forum]

Hello 

 I have created a custom bridge and I am connecting NIOS II/e processor to On chip RAM using the custom bridge. However, while selecting the memory for reset vector and exception vector, On-chip RAM is not identified and instead my custom bridge is identified. Contrary to the Avalon MM pipeline bridge or any other bridge from Altera library, the bridge is never identified as memory device and instead the memory connected on the Master interface of bridge is identified.  Please help me configure my bridge so that the memory connected on its master port is identified as memory for CPU instead of the bridge itself.

[Altera_Forum]

There is an extra line you need to the .tcl file to let Qsys know that it's a bridge: 

 set_interface_property <slave_name> bridgesToMaster <master_name>   When you have this line set Qsys will treat the component as a 'transparent' type of IP so the slaves downstream from your bridge should show up instead of the bridge itself.

[Altera_Forum]

Thank you BadOmen, my problem is solved by using the above line as mentioned.