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One design to explain all timing constraints: Help needed.

Altera_Forum
Honored Contributor II
804 Views

I am trying to come up with some sort of representative (and a very simple) design to illustrate how and when ALL the timing constraints are used. I need some help. Upon completion of individual parts, I'll upload the design (I'll combine them to make it look like one big design) with annotations explaining why certain timing constraint is used. 

 

Can anyone upload a diagram that illustrates just one usage of a timing constraint? No equations, no specific details, just a very high level view. I've uploaded mine just to give an idea on what we should be working towards.... 

 

I got this example from some other forum...
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2 Replies
Altera_Forum
Honored Contributor II
80 Views

Hi, 

 

Below link provided best explanation, which may help you. 

Complete STA: 

http://www.vlsi-expert.com/2011/02/timing-analysis-basis-what-and-why.html 

OVC : 

[URL]https://www.youtube.com/watch?v=AGF7bt5p6r4&index=1&list=PLUSK3BZWA60uEbKzWP6SST8MwkQ-0GOrs[URL] 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
80 Views

Thank you.

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