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Altera_Forum
Honored Contributor I
1,356 Views

OpenCL Emulator on Cyclone V

Cheers, 

 

Currently, I am trying to emulate an OpenCL design example using the Intel FPGA SDK for OpenCL Emulator on a Cyclone V. However there is a remark in the getting starting guide: "Emulation is a Linux-only optional step when setting up the SDK for use with ®SoC FPGAs. Specifically, you must emulate your OpenCL kernel on a non-SoC FPGA board before executing your kernel on the SoC FPGA." Does this mean that I have to emulate my OpenCL kernel on a non-SoC FPGA before be able to emulate the whole implementation on my computer? Thank you very much 

 

Kind Regards
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5 Replies
Altera_Forum
Honored Contributor I
86 Views

Are you targeting an SoC variant of Cyclone V for your kernel design? 

 

The emulator just requires you to target an installed BSP. If you have a BSP for your board installed (which one?), then just try it to see if it works.
Altera_Forum
Honored Contributor I
86 Views

 

--- Quote Start ---  

Are you targeting an SoC variant of Cyclone V for your kernel design? 

 

The emulator just requires you to target an installed BSP. If you have a BSP for your board installed (which one?), then just try it to see if it works. 

--- Quote End ---  

 

 

Thank you very much for replying the question :D. I think that you misunderstand my problem. For clarify the thing I will describe the process and the problems. 

 

I am developing over the SOC-FPGA Cyclone V (Cyclone V SoC Development Kit) a OpenCL application which is composed of two application, host and kernel application. The host application will run inside of the SOC part, and the kernel application will run in FPGA part of Cyclone V. I am following the getting started guide of Intel OpenCL SDK for this board, and everything works perfect.  

 

A full compilation could take hours, and this is a important waste of time for a continuously developing. Trying to use wisely the time, now I am following the approach of emulation, which consist in not to do a full compilation, and test the syntax and operation using emulation of the project.  

 

Issues related to this are following: 

- Emulation is only linux process, and in this moment I have license for windows Intel OpenCL SDK, so change to linux is not easy at all. 

- The guide is not clear for me since it said that the emulation of the kernel will be done on non-SOC FPGA which for me means a FPGA pure, and I just have the Cyclone V board. 

- I am understanding that emulation part needs a extra FPGA conected to computer by using PCI express, and on this way, the kernel will be emulated in FPGA and the host application in linux. It is my interpretation of the guide. 

 

I will appreciate if you can clarify all my doubts. 

 

I attach the documentation that I'm using: 

https://www.altera.com/en_us/pdfs/literature/hb/opencl-sdk/aocl_c5soc_getting_started.pdf (page 38) 

 

PD: I am thinking in a possible solution for improve the development time which consists in develop the application over my laptop using OpenCL Intel SDK for x86/x64 processor without be worried for hardware accdelration and focus on the correct functionality of the code, and then make a full compilation for cyclone V wasting the time needed and changing the focus to hardware acceleration results. However, extra issues rise, as the Intel OpenCL SDK for x86/x64 processors uses OpenCL version 2.0 and the supported version for the cyclone V is 1.0. I did a question related to a version of SDK with OpenCL 1.0 in Intel forums (https://software.intel.com/en-us/forums/opencl/topic/740813) for conclude if this approach is possible or not. However if you have a suggestion or know a different approach for development, let me know. I will be deeply thankful.
Altera_Forum
Honored Contributor I
86 Views

Emulation is not Linux only. Just issue: 

 

aoc -march=emulator --board <board> <.cl file> 

 

And then run your executable host code. 

 

You have to set up an environmental variable: 

 

set CL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number of devices> 

 

For emulation, you do not need any hardware connected. That's the point of it being an emulator! 

 

You're just emulating the kernel function, so even if eventually you'll be using the ARM processor as host, you can still emulate to test the functionality of your kernel and the correctness of your host code, not to mention checking the optimization report to see what you can improve before doing a potentially multi-hour compile. 

 

As far as compatibility, Altera's OpenCL is 1.0 compliant (not 2.0), but supports some of later versions' features, like pipes. In any case, it is backwards compatible, so there are no issues there. 

 

Just try it! It'll work.
Altera_Forum
Honored Contributor I
86 Views

Thank you very much sstrell!

Altera_Forum
Honored Contributor I
86 Views

I am in the process of emulating too. I will comment my case and probably open a new thread. 

 

I tried your idea, sstrell, of emulating using the ARM processor. It doesn't work for me (did it for you, alviur?). And in fact it makes sense to me it failing, since the kernel "program" was built for an emulator, not a real board, which is in fact what the error message issues: 

 

root@socfpga:~/testemul# ./host Querying platform for info: ========================== CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM) CL_PLATFORM_VENDOR = Altera Corporation CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.0 Querying device for info: ======================== CL_DEVICE_NAME = de1soc_sharedonly : Cyclone V SoC Development Kit CL_DEVICE_VENDOR = Intel(R) Corporation CL_DEVICE_VENDOR_ID = 4466 CL_DEVICE_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.0 CL_DRIVER_VERSION = 17.0 CL_DEVICE_ADDRESS_BITS = 64 CL_DEVICE_AVAILABLE = true CL_DEVICE_ENDIAN_LITTLE = true CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768 CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0 CL_DEVICE_GLOBAL_MEM_SIZE = 536870912 CL_DEVICE_IMAGE_SUPPORT = true CL_DEVICE_LOCAL_MEM_SIZE = 16384 CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000 CL_DEVICE_MAX_COMPUTE_UNITS = 1 CL_DEVICE_MAX_CONSTANT_ARGS = 8 CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 134217728 CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3 CL_DEVICE_MEM_BASE_ADDR_ALIGN = 8192 CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024 CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4 CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2 CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0 Command queue out of order? = false Command queue profiling enabled? = true Using AOCX: hello_world.aocx Context callback: Program was compiled for a different board. aocx is for board EmulatorDevice whereas device is de1soc_sharedonly Use aocl program to safely transition to the new board . Context callback: Invalid binary ERROR: CL_INVALID_BINARY Location: ../common/src/AOCLUtils/opencl.cpp:392 Failed to create program with binary root@socfpga:~/testemul#  

 

Anyway, part of the idea of emulation, besides saving the synthesis time, is the possibility to debug your application from the development systems. The idea of Intel is precisely this, and this is why you need to target a non SoC board. When the guide directs you to (page 38, https://www.altera.com/en_us/pdfs/literature/hb/opencl-sdk/aocl_c5soc_getting_started.pdf): 

 

Emulation is a Linux-only optional step when setting up the SDK for use with ® SoC 

FPGAs. Specifically, you must emulate your OpenCL kernel on a non-SoC FPGA board 

before executing your kernel on the SoC FPGA. 

 

1. Install a Custom or Reference Platform because emulation targets a specific FPGA 

board. 

 

the idea is using one of the standard boards that comes within the SDK installation (I guess). This is the same the tutorial I attended to in a conference was doing (targetting the s5_ref board for emulation)...I guess it just needs some info on a device/platform to build the kernel.  

 

I did in fact try to do it, but I guess a weird error when building the host application: 

 

rusa@emma ~/dev/IntelFPGA/OpenCL/examples/hello_world $ make /home/rusa/tools/intelFPGA/17.0/hld/board/s5_ref/linux64/lib/libaltera_s5_ref_mmd.so: file not recognized: File format not recognized collect2: error: ld returned 1 exit status Makefile:74: recipe for target 'bin/host' failed make: *** Error 1  

 

My init scripts are working fine, and the file is itself there but with an unrecognized format. I even tried to grab it again from the RTE (both in the initial 17.0 version and the Update 2), and the same error again. I will open a support ticket and probably a thread here, since I cannot find any previous same issue. 

 

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