Verilog real functions and compile time

[Altera_Forum]

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. 

 I have a function which returns a real value, and takes in real values for arguments, let's call this f_real( x ). The purpose of this function is to calculate a LUT at compile time. The inputs to the function are constants/static, and the output is assigned to a signed [15:0] register.  Quartus II gives me an error stating that "real variable data types are not supported". I understand for synthesis, I cannot have a module which takes in real or outputs real values, but I am explicitly just calling a function which I hope to be evaluated. I know I can do this in VHDL, but I'd like to be able to perform the same operation in Verilog as the rest of the project is in Verilog.  So, in conclusion, is it at all possible to use a function which takes in real values and returns real values to be evaluated at compile time using Verilog in Quartus II?

[Altera_Forum]

Sorry, but that's not clear to me. Does the module output a 16 bit vector or a real variable? Real variables cannot be uses for synthesis, thats true.

[Altera_Forum]

Outputs to a vector. 

 Example code:  module math_real_test ( output signed y ) ; function real f_real ; input real x ; begin f_real = 5.74857*(x + 0.7071) ; end endfunction assign y = $rtoi(4096.0*f_real(1.0)) ; endmoduleI am used to the strict typing of VHDL, so I don't know if the $rtoi is required or even necessary.

[Altera_Forum]

I am not very familiar with VHDL but I a pretty sure that this is not sythesizable, neither in VHDL nor in Verilog. For me it looks as if you write testbench code. But a testbench is not intended to by systhesized. It's only used in simulation. What do you really want to implement in the FPGA?

[Altera_Forum]

I am trying to generate a compile-time specified LUT based on static inputs. 

 You are incorrect in that it is not synthesizable in VHDL. The code below will synthesize with no problems and yield warnings stating the output is stuck at VCC or GND - which is understandable since it obviously doesn't change.  library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.math_real.all ; entity math_real_test is port ( y : out signed(31 downto 0) ) ; end entity ; -- math_real_test architecture arch of math_real_test is function f_real( x : in real ) return real is begin return 5.74857*(x + 0.7071) ; end function ; begin y <= to_signed( integer(4096.0 * f_real( 1.0 )), y'length ) ; end architecture ; -- arch  Are there any other questions or suggestions you may have as to being able to do this in Verilog? Should I be looking at SystemVerilog instead of regular Verilog?

[Altera_Forum]

Ok, now I understand what you want to do. Try this: 

 module math_real_test (y); output [31:0] y;   function [31:0] f_real; input [31:0] x ; f_real = 5.74857 * (x + 0.7071) ; endfunction   assign y = 4096 * f_real(1);   endmodule

[Altera_Forum]

That works, but it removes my ability to pass in a real value which is required. 

 The function should be able to be passed real values and return real values, which are then scaled, rounded and/or truncated appropriately.  Any other ideas?

[Altera_Forum]

Well, it seems as if this is a limitation of the Quartus synthesis. Sorry, no further ideas.

[Altera_Forum]

Maybe you can use a simple text macro instead of a function? 

 module math_real_test (y); output [31:0] y;  `define f_real 5.74857 * (0.7071 + `x)  `define x 1.2 assign y = 4096 * `f_real;  endmodule

[Altera_Forum]

Thanks for the help, unfortunately that doesn't seem to help me much. 

 In the end, I wanted to perform trig functions which I had written in Verilog. I basically re-created math_real from VHDL in Verilog, but the lack of real number capabilities in Quartus II puts a damper on using it for synthesis and keeps its use to simulation only.

[Altera_Forum]

Maybe you can help me to understand what the VHDL code does. To my understanding it assigns a 32 bit signed integer value to port y. The value to be assigned is the result of a operation of data type real that is converted to integer before assigning. The verilog code does the same, and it can be systhesized. So, where is the difference?

[Altera_Forum]

Taking a more real scenario, lets say I want to make a LUT of fixed-point values representing 1/sqrt(x). Finding sqrt(x) is as easy as raising x^0.5. Raising x^0.5 is done by using exp(0.5 * ln(x)) - each of which should not lose precision by truncating and rounding for every return. 

 In the end, while the code you provided does work for trivial cases (which I had asked about), once the LUT gets a little more complicated, it all seems to fall apart.  The conclusion is that Quartus II does not support functions that return real types, even if they are only evaluated at compile time, which is a shame.

[Altera_Forum]

I think the Quartus error message help really says it all here! 

 Error (10172): Verilog HDL unsupported feature error at x.v(6): real variable data type values are not supported   Verilog HDL unsupported feature error at <location>: real variable data type values are not supported  -------------------------------------------------------------------------------- CAUSE: In a Verilog Design File (.v) at the specified location, you declared a real variable data type. although verilog hdl supports real variable data types, this type is not supported in the quartus ii software.   ACTION: Change the data type of the variable to something other than real.

[Altera_Forum]

--- Quote Start ---  I think the Quartus error message help really says it all here!  Error (10172): Verilog HDL unsupported feature error at x.v(6): real variable data type values are not supported   Verilog HDL unsupported feature error at <location>: real variable data type values are not supported  -------------------------------------------------------------------------------- CAUSE: In a Verilog Design File (.v) at the specified location, you declared a real variable data type. although verilog hdl supports real variable data types, this type is not supported in the quartus ii software.   ACTION: Change the data type of the variable to something other than real.  --- Quote End ---    If the function were used after compilation time and active in the design itself, then I would understand Quartus II getting upset - but the fact of the matter is that each real function call I perform gets collapsed down to a constant, static value. In other words, to allow for reusable code and a greater number of built-time parameters, I want to use Quartus II as a fancy calculator. It is obviously capable of performing operations (at compile time) on real numbers. Quartus II should error only if:   - Non-static real values are being evaluated by a function  - A real is declared as a port input or output  Otherwise, it's just a macro - right? Even if you assign a real value to an array of wires, Verilog isn't strictly typed so it should just perform the conversion - right?

[Altera_Forum]

I see exactly what you are trying to do and agree that it seems reasonable to assume that Quartus should be able to reduce your functions at compile time. 

 However, it doesn't support it....yet! So probably time to move on and solve the problem in another way. :rolleyes:

[Altera_Forum]

The missing support of real data type is common to a number of Verilog synthesis tools, not just special to Quartus. The structural differences between the languages may be reason, I don't know exactly. I'm also not sure, if the extensive support of real compile-time operations in Quartus VHDL exists in other synthesis tools, at least real is marked as unsupported e.g in the Synopsis VHDL reference manual.  

 But also the Quartus compile time features for VHDL aren't documented in detail, you have to find out by yourself. Personally I'm happy with my favourite VHDL language, a colleague who generally prefers Verilog has started to use mixed language designs with VHDL components for special purposes.

[Altera_Forum]

Even if Quartus systhesis would support the real data type completety it would not help Bpadalino to do what he wants to. Verilog itself supports only a few operators for the real data type. Definitely no sqrt, exp or ln. 

 Bpadalino, my recommndation for you: Use a memory module and initialize is with a hex file. Generate the hex file with a simpe C programm that calculates the data. Verilog isn't made for this stuff.

[Altera_Forum]

Or use a VHDL component, if you want to have all calculations inside the Quartus project.

[Altera_Forum]

--- Quote Start ---  Even if Quartus systhesis would support the real data type completety it would not help Bpadalino to do what he wants to. Verilog itself supports only a few operators for the real data type. Definitely no sqrt, exp or ln.   Bpadalino, my recommndation for you: Use a memory module and initialize is with a hex file. Generate the hex file with a simpe C programm that calculates the data. Verilog isn't made for this stuff.  --- Quote End ---  I wrote said functions in Verilog to have something similar to ieee.math_real, except to be in Verilog. I was quite disappointed when those functions were only useful for simulation.  I really am just trying to avoid using C, Perl, Python, or any other external programming language to complicate matters even more.    --- Quote Start ---  Or use a VHDL component, if you want to have all calculations inside the Quartus project.  --- Quote End ---  I'd prefer to stay away from mixed-mode HDL, and oftentimes it isn't an option (for me) to mix.  I really wanted to try to be as language agnostic as possible, but it seems I'll stick with VHDL as my language preference. For my purposes, it seems that Verilog is just too limited.

[Altera_Forum]

Unfortunately more than a year has passed, and this "bug" is still there :(

[Altera_Forum]

you should file an enhancement request with Altera. 

 that said after i started using HDL only to describe hardware and not using it as a scripting language i became much happier. not an ideal solution, but...