I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues.
I have a function which returns a real value, and takes in real values for arguments, let's call this f_real( x ). The purpose of this function is to calculate a LUT at compile time. The inputs to the function are constants/static, and the output is assigned to a signed [15:0] register.
Quartus II gives me an error stating that "real variable data types are not supported". I understand for synthesis, I cannot have a module which takes in real or outputs real values, but I am explicitly just calling a function which I hope to be evaluated. I know I can do this in VHDL, but I'd like to be able to perform the same operation in Verilog as the rest of the project is in Verilog.
So, in conclusion, is it at all possible to use a function which takes in real values and returns real values to be evaluated at compile time using Verilog in Quartus II?
