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Optimizing a set of registers

Altera_Forum
Honored Contributor II
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I am working on optimizing a processor I made (size-wise) and I noticed that the register set is quite large (about 1000 LEs) I looked into the sysnthesized logic using the RTL viewer and it looked very messy (I am trying to upload an image of it) with over 100 multiplexers and lots of unnecessary signals. 

 

I am wondering how I can make it so the design is simpler (i.e. the logic is composed of the register, two multiplexers [for reads], and one de-multiplexer [for writing]). 

 

The VHDL code I used is listed here: 

 

entity default_registers is port ( input : in std_logic_vector(31 downto 0); register_to_write : in std_logic_vector (4 downto 0); write_to_register : in std_logic; register_to_read_a : in std_logic_vector (4 downto 0); register_to_read_b : in std_logic_vector (4 downto 0); clk : in std_logic; clear: in std_logic; output0 : out std_logic_vector(31 downto 0); output1 : out std_logic_vector(31 downto 0) ); end default_registers; architecture Behavioral of default_registers is signal register1 : std_logic_vector (31 downto 0); signal register2 : std_logic_vector (31 downto 0); signal register3 : std_logic_vector (31 downto 0); signal register4 : std_logic_vector (31 downto 0); signal register5 : std_logic_vector (31 downto 0); signal register6 : std_logic_vector (31 downto 0); signal register7 : std_logic_vector (31 downto 0); signal register8 : std_logic_vector (31 downto 0); signal register9 : std_logic_vector (31 downto 0); signal register10 : std_logic_vector (31 downto 0); signal register11 : std_logic_vector (31 downto 0); signal register12 : std_logic_vector (31 downto 0); signal register13 : std_logic_vector (31 downto 0); signal register14 : std_logic_vector (31 downto 0); signal register15 : std_logic_vector (31 downto 0); signal register16 : std_logic_vector (31 downto 0); signal register17 : std_logic_vector (31 downto 0); signal register18 : std_logic_vector (31 downto 0); signal register19 : std_logic_vector (31 downto 0); signal register20 : std_logic_vector (31 downto 0); signal register21 : std_logic_vector (31 downto 0); signal register22 : std_logic_vector (31 downto 0); signal register23 : std_logic_vector (31 downto 0); signal register24 : std_logic_vector (31 downto 0); signal register25 : std_logic_vector (31 downto 0); signal register26 : std_logic_vector (31 downto 0); signal register27 : std_logic_vector (31 downto 0); signal register28 : std_logic_vector (31 downto 0); signal register29 : std_logic_vector (31 downto 0); signal register30 : std_logic_vector (31 downto 0); signal register31 : std_logic_vector (31 downto 0); begin process(clear, clk, write_to_register) begin if clear = '1' then register1 <= (others => '0'); register2 <= (others => '0'); register3 <= (others => '0'); register4 <= (others => '0'); register5 <= (others => '0'); register6 <= (others => '0'); register7 <= (others => '0'); register8 <= (others => '0'); register9 <= (others => '0'); register10 <= (others => '0'); register11 <= (others => '0'); register12 <= (others => '0'); register13 <= (others => '0'); register14 <= (others => '0'); register15 <= (others => '0'); register16 <= (others => '0'); register17 <= (others => '0'); register18 <= (others => '0'); register19 <= (others => '0'); register20 <= (others => '0'); register21 <= (others => '0'); register22 <= (others => '0'); register23 <= (others => '0'); register24 <= (others => '0'); register25 <= (others => '0'); register26 <= (others => '0'); register27 <= (others => '0'); register28 <= (others => '0'); register29 <= (others => '0'); register30 <= (others => '0'); register31 <= (others => '0'); elsif falling_edge(clk) then if write_to_register = '1' then case register_to_write is when "00000" => -- Do nothing since register0 is always zero when "00001" => register1 <= input; when "00010" => register2 <= input; when "00011" => register3 <= input; when "00100" => register4 <= input; when "00101" => register5 <= input; when "00110" => register6 <= input; when "00111" => register7 <= input; when "01000" => register8 <= input; when "01001" => register9 <= input; when "01010" => register10 <= input; when "01011" => register11 <= input; when "01100" => register12 <= input; when "01101" => register13 <= input; when "01110" => register14 <= input; when "01111" => register15 <= input; when "10000" => register16 <= input; when "10001" => register17 <= input; when "10010" => register18 <= input; when "10011" => register19 <= input; when "10100" => register20 <= input; when "10101" => register21 <= input; when "10110" => register22 <= input; when "10111" => register23 <= input; when "11000" => register24 <= input; when "11001" => register25 <= input; when "11010" => register26 <= input; when "11011" => register27 <= input; when "11100" => register28 <= input; when "11101" => register29 <= input; when "11110" => register30 <= input; when "11111" => register31 <= input; when others => end case; end if; end if; end process; process (register_to_read_a, register_to_read_b) begin case register_to_read_a is when "00000" => output0 <= (others => '0'); when "00001" => output0 <= register1; when "00010" => output0 <= register2; when "00011" => output0 <= register3; when "00100" => output0 <= register4; when "00101" => output0 <= register5; when "00110" => output0 <= register6; when "00111" => output0 <= register7; when "01000" => output0 <= register8; when "01001" => output0 <= register9; when "01010" => output0 <= register10; when "01011" => output0 <= register11; when "01100" => output0 <= register12; when "01101" => output0 <= register13; when "01110" => output0 <= register14; when "01111" => output0 <= register15; when "10000" => output0 <= register16; when "10001" => output0 <= register17; when "10010" => output0 <= register18; when "10011" => output0 <= register19; when "10100" => output0 <= register20; when "10101" => output0 <= register21; when "10110" => output0 <= register22; when "10111" => output0 <= register23; when "11000" => output0 <= register24; when "11001" => output0 <= register25; when "11010" => output0 <= register26; when "11011" => output0 <= register27; when "11100" => output0 <= register28; when "11101" => output0 <= register29; when "11110" => output0 <= register30; when "11111" => output0 <= register31; when others => end case; case register_to_read_b is when "00000" => output1 <= (others => '0'); when "00001" => output1 <= register1; when "00010" => output1 <= register2; when "00011" => output1 <= register3; when "00100" => output1 <= register4; when "00101" => output1 <= register5; when "00110" => output1 <= register6; when "00111" => output1 <= register7; when "01000" => output1 <= register8; when "01001" => output1 <= register9; when "01010" => output1 <= register10; when "01011" => output1 <= register11; when "01100" => output1 <= register12; when "01101" => output1 <= register13; when "01110" => output1 <= register14; when "01111" => output1 <= register15; when "10000" => output1 <= register16; when "10001" => output1 <= register17; when "10010" => output1 <= register18; when "10011" => output1 <= register19; when "10100" => output1 <= register20; when "10101" => output1 <= register21; when "10110" => output1 <= register22; when "10111" => output1 <= register23; when "11000" => output1 <= register24; when "11001" => output1 <= register25; when "11010" => output1 <= register26; when "11011" => output1 <= register27; when "11100" => output1 <= register28; when "11101" => output1 <= register29; when "11110" => output1 <= register30; when "11111" => output1 <= register31; when others => end case; end process; end Behavioral;
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Altera_Forum
Honored Contributor II
778 Views

you can readily use two rams each with 5 bit address. you write input to both rams(same copy). you then read out to output0 and output1 from ram1,ram2. 

 

otherwise your logic is ok but I will register the outputs
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

you can readily use two rams each with 5 bit address. you write input to both rams(same copy). you then read out to output0 and output1 from ram1,ram2. 

--- Quote End ---  

 

 

Can the ram be implemented directly in the VHDL code in a method that won't require making another file (or component if possible)? 

 

 

--- Quote Start ---  

 

otherwise your logic is ok but I will register the outputs 

 

--- Quote End ---  

 

 

My outputs are registered in a different component that is external of the one that I have posted.
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

Can the ram be implemented directly in the VHDL code in a method that won't require making another file (or component if possible)? 

 

 

 

My outputs are registered in a different component that is external of the one that I have posted. 

--- Quote End ---  

 

 

yes you can infer ram in vhdl code for either one port or dual port. There are templates from altera and possibly quartus for that.
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Altera_Forum
Honored Contributor II
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One question: Wouldn't using 2 ram blocks take up more space than needed if I was to just use 2 multiplexors, 1 de-multiplexor, and 31 (not 32 as register 0 is always 0) registers?

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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

One question: Wouldn't using 2 ram blocks take up more space than needed if I was to just use 2 multiplexors, 1 de-multiplexor, and 31 (not 32 as register 0 is always 0) registers? 

--- Quote End ---  

 

 

you are using 31 x 32 = 992 registers(flops). 

you are also using a lot of logic. 

This is not wrong if indeed you need access to several registers at same time. But since you access one at a time then a ram can do it. 

two dedicated rams take no logic in the fabric apart from addressing. They are already there in the fpga empty.
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

you are using 31 x 32 = 992 registers(flops). 

you are also using a lot of logic. 

This is not wrong if indeed you need access to several registers at same time. But since you access one at a time then a ram can do it. 

two dedicated rams take no logic in the fabric apart from addressing. They are already there in the fpga empty. 

--- Quote End ---  

 

 

I am reading two values at once from the regiser file so I assume logic would be the better choice. Is there any way to use my write selector as a selector for a de-multiplexor that connects to the write port of every register. The input to the demultiplexor would be write_to register signal. 

 

I also don't want to use ram as I am using a large amount of it for my caches.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Is there any way to use my write selector as a selector for a de-multiplexor that connects to the write port of every register. The input to the demultiplexor would be write_to register signal. 

 

--- Quote End ---  

 

 

I don't quite get it, you are already doing that.
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

I don't quite get it, you are already doing that. 

--- Quote End ---  

 

 

It doesn't seem to be doing it that way in the RTL viewer though. I will post a pciture when I can to show the issue (tommorow).
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Altera_Forum
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here (http://i.imgur.com/vhf2qc6.png) is my relatively rubbish picture of a portion of the circuit that I could upload. Please note the large number of muxes that there are. There seem to be too many of them. 

 

Edit: On a side note, I am wondering how you can have multiple buses go to one output (same width as each bus). I am currently ORing the buses together, but it takes up a large number of LEs.
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Altera_Forum
Honored Contributor II
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If you would get rid of the 'clear' signal you could implement this register bank with a dual port memory. 

You just need to test for address zero and prevent a write to the memory when this address is selected. 

 

But as long as a your 'clear' signal is required you will end up with 31*32 = 992 registers and two big 32 bit wide 31:1 multiplexers.
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

If you would get rid of the 'clear' signal you could implement this register bank with a dual port memory.You just need to test for address zero and prevent a write to the memory when this address is selected.But as long as a your 'clear' signal is required you will end up with 31*32 = 992 registers and two big 32 bit wide 31:1 multiplexers. 

--- Quote End ---  

Only issue with that is that I want my registers to clear when the signal is asserted.
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Altera_Forum
Honored Contributor II
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You could reset the dual port memory but not in one clock cycle. You just need to issue 31 writes with zero data to it and increment the address from 1 to 31 for each write.

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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

You could reset the dual port memory but not in one clock cycle. You just need to issue 31 writes with zero data to it and increment the address from 1 to 31 for each write. 

--- Quote End ---  

 

 

I prefer using registers as ram is a vital resource I need to preserve. I am wondering why my rtl viewer is giving such a complicated diagram for a simple vhdl file.
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Altera_Forum
Honored Contributor II
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Oh, if this is your problem, belief me you are not alone. The Altera RTL viewer is the worst I have ever seen so far and I'm already more than 15 years in this industry.

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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

I prefer using registers as ram is a vital resource I need to preserve. I am wondering why my rtl viewer is giving such a complicated diagram for a simple vhdl file. 

--- Quote End ---  

 

 

You may try recoding as follows (you may get some 20% reduction or so) 

for write side declare 31 internal signals for switches: sw1 ~ sw31 

 

-- comb. a <= wr_addr(4); b <= wr_addr(3); c <= wr_addr(2); d <= wr_addr(1); e <= wr_addr(0); sw1 <= not a and not b and not c and not d and e and wr; --00001 sw2 <= not a and not b and not c and d and not e and wr; --00010 sw3 <= not a and not b and not c and d and e and wr; --00011 sw4 <= not a and not b and c and not d and not e and wr; --00100 process... elsif falling_edge(clk) then if sw1 = '1' then register1 <= input; end if; if sw2 = '1' then register2 <= input; end if; if sw3 = '1' then register3 <= input; end if; if sw4 = '1' then register4 <= input; end if; ...etc  

 

for outputs do same decoding logic on address but connect say sw1 ANDed with all 32 bits of reg1 output, sw2 ANDed with reg2 output and so on... connect all 31 ANDed outputs(31 x 32bits !!) ORed into 32 output bits.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

You may try recoding as follows (you may get some 20% reduction or so) 

for write side declare 31 internal signals for switches: sw1 ~ sw31 

 

-- comb. a <= wr_addr(4); b <= wr_addr(3); c <= wr_addr(2); d <= wr_addr(1); e <= wr_addr(0); sw1 <= not a and not b and not c and not d and e and wr; --00001 sw2 <= not a and not b and not c and d and not e and wr; --00010 sw3 <= not a and not b and not c and d and e and wr; --00011 sw4 <= not a and not b and c and not d and not e and wr; --00100 process... elsif falling_edge(clk) then if sw1 = '1' then register1 <= input; end if; if sw2 = '1' then register2 <= input; end if; if sw3 = '1' then register3 <= input; end if; if sw4 = '1' then register4 <= input; end if; ...etc  

 

for outputs do same decoding logic on address but connect say sw1 ANDed with all 32 bits of reg1 output, sw2 ANDed with reg2 output and so on... connect all 31 ANDed outputs(31 x 32bits !!) ORed into 32 output bits. 

--- Quote End ---  

 

 

I will try this. It seems like it will work, but it is more code then I really want to do.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I will try this. It seems like it will work, but it is more code then I really want to do. 

--- Quote End ---  

 

 

here is my code, see what is the difference in resource. 

 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity test is port ( clear : in std_logic; clk : in std_logic; input : in std_logic_vector(31 downto 0); wr : in std_logic; wr_addr : in std_logic_vector (4 downto 0); rd_addr_a : in std_logic_vector (4 downto 0); rd_addr_b : in std_logic_vector (4 downto 0); output0 : out std_logic_vector(31 downto 0); output1 : out std_logic_vector(31 downto 0) ); end test; architecture Behavioral of test is signal wr_sw, rda_sw,rdb_sw : std_logic_vector(30 downto 0); type type1 is array(0 to 30) of std_logic_vector(31 downto 0); signal regs : type1; signal anded_a, anded_b : type1; component address_decode port( address : in std_logic_vector(4 downto 0); wr : in std_logic; sw : out std_logic_vector(30 downto 0) ); end component; begin wr_decode: address_decode port map( address => wr_addr, wr => wr, sw => wr_sw ); rda_decode: address_decode port map( address => rd_addr_a, wr =>'1', sw => rda_sw ); rdb_decode: address_decode port map( address => rd_addr_b, wr => '1', sw => rdb_sw ); -- write process(clear, clk) begin if clear = '1' then regs <= (others => (others =>'0')); elsif falling_edge(clk) then for i in 0 to 30 loop if wr_sw(i) = '1' then regs(i) <= input; end if; end loop; end if; end process; -- read process(rda_sw,rdb_sw,regs,anded_a,anded_b) begin for i in 0 to 30 loop if rda_sw(i) = '1' then anded_a(i) <= regs(i); else anded_a(i) <= (others=> '0'); end if; if rdb_sw(i) = '1' then anded_b(i) <= regs(i); else anded_b(i) <= (others=> '0'); end if; end loop; output0 <= anded_a(0) or anded_a(1) or anded_a(2) or anded_a(3) or anded_a(4) or anded_a(5) or anded_a(6) or anded_a(7) or anded_a(8) or anded_a(9) or anded_a(10) or anded_a(11) or anded_a(12) or anded_a(13) or anded_a(14) or anded_a(15) or anded_a(16) or anded_a(17) or anded_a(18) or anded_a(19) or anded_a(20) or anded_a(21) or anded_a(22) or anded_a(23) or anded_a(24) or anded_a(25) or anded_a(26) or anded_a(27) or anded_a(28) or anded_a(29) or anded_a(30); output1 <= anded_b(0) or anded_b(1) or anded_b(2) or anded_b(3) or anded_b(4) or anded_b(5) or anded_b(6) or anded_b(7) or anded_b(8) or anded_b(9) or anded_b(10) or anded_b(11) or anded_b(12) or anded_b(13) or anded_b(14) or anded_b(15) or anded_b(16) or anded_b(17) or anded_b(18) or anded_b(19) or anded_b(20) or anded_b(21) or anded_b(22) or anded_b(23) or anded_b(24) or anded_b(25) or anded_b(26) or anded_b(27) or anded_b(28) or anded_b(29) or anded_b(30); end process; end Behavioral;  

 

and this component 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity address_decode is port( address : in std_logic_vector(4 downto 0); wr : in std_logic; sw : out std_logic_vector(30 downto 0) ); end entity; architecture arch1 of address_decode is signal a,b,c,d,e : std_logic; begin a <= address(4); b <= address(3); c <= address(2); d <= address(1); e <= address(0); sw(0) <= not a and not b and not c and not d and e and wr; --00001 sw(1) <= not a and not b and not c and d and not e and wr; --00010 sw(2) <= not a and not b and not c and d and e and wr; --00011 sw(3) <= not a and not b and c and not d and not e and wr; --00100 sw(4) <= not a and not b and c and not d and e and wr; --00101 sw(5) <= not a and not b and c and d and not e and wr; --00110 sw(6) <= not a and not b and c and d and e and wr; --00111 sw(7) <= not a and not b and not c and not d and e and wr; --01000 sw(8) <= not a and b and not c and not d and not e and wr; --01001 sw(9) <= not a and b and not c and d and not e and wr; --01010 sw(10) <= not a and b and not c and d and e and wr; --01011 sw(11) <= not a and b and c and not d and not e and wr; --01100 sw(12) <= not a and b and c and not d and e and wr; --01101 sw(13) <= not a and b and not c and d and e and wr; --01110 sw(14) <= not a and b and c and d and e and wr; --01111 sw(15) <= a and not b and not c and not d and not e and wr;--10000 sw(16) <= a and not b and not c and not d and e and wr; --10001 sw(17) <= a and not b and not c and d and not e and wr; --10010 sw(18) <= a and not b and not c and d and e and wr; --10011 sw(19) <= a and not b and c and not d and not e and wr; --10100 sw(20) <= a and not b and c and not d and e and wr; --10101 sw(21) <= a and not b and c and d and not e and wr; --10110 sw(22) <= a and not b and c and d and e and wr; --10111 sw(23) <= a and b and not c and not d and not e and wr; --11000 sw(24) <= a and b and not c and not d and e and wr; --11001 sw(25) <= a and b and not c and d and not e and wr; --11010 sw(26) <= a and b and not c and d and e and wr; --11011 sw(27) <= a and b and c and not d and not e and wr; --11100 sw(28) <= a and b and c and not d and e and wr; --11101 sw(29) <= a and b and c and d and not e and wr; --11110 sw(30) <= a and b and c and d and e and wr; --11111 end arch1;
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Altera_Forum
Honored Contributor II
778 Views

it looks like resource varies according to device and may get better or worse. But rtl viewer looks cleaner. 

The write side gets better certainly but read side is massive
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Altera_Forum
Honored Contributor II
778 Views

 

--- Quote Start ---  

here is my code, see what is the difference in resource. 

 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity test is port ( clear : in std_logic; clk : in std_logic; input : in std_logic_vector(31 downto 0); wr : in std_logic; wr_addr : in std_logic_vector (4 downto 0); rd_addr_a : in std_logic_vector (4 downto 0); rd_addr_b : in std_logic_vector (4 downto 0); output0 : out std_logic_vector(31 downto 0); output1 : out std_logic_vector(31 downto 0) ); end test; architecture Behavioral of test is signal wr_sw, rda_sw,rdb_sw : std_logic_vector(30 downto 0); type type1 is array(0 to 30) of std_logic_vector(31 downto 0); signal regs : type1; signal anded_a, anded_b : type1; component address_decode port( address : in std_logic_vector(4 downto 0); wr : in std_logic; sw : out std_logic_vector(30 downto 0) ); end component; begin wr_decode: address_decode port map( address => wr_addr, wr => wr, sw => wr_sw ); rda_decode: address_decode port map( address => rd_addr_a, wr =>'1', sw => rda_sw ); rdb_decode: address_decode port map( address => rd_addr_b, wr => '1', sw => rdb_sw ); -- write process(clear, clk) begin if clear = '1' then regs <= (others => (others =>'0')); elsif falling_edge(clk) then for i in 0 to 30 loop if wr_sw(i) = '1' then regs(i) <= input; end if; end loop; end if; end process; -- read process(rda_sw,rdb_sw,regs,anded_a,anded_b) begin for i in 0 to 30 loop if rda_sw(i) = '1' then anded_a(i) <= regs(i); else anded_a(i) <= (others=> '0'); end if; if rdb_sw(i) = '1' then anded_b(i) <= regs(i); else anded_b(i) <= (others=> '0'); end if; end loop; output0 <= anded_a(0) or anded_a(1) or anded_a(2) or anded_a(3) or anded_a(4) or anded_a(5) or anded_a(6) or anded_a(7) or anded_a(8) or anded_a(9) or anded_a(10) or anded_a(11) or anded_a(12) or anded_a(13) or anded_a(14) or anded_a(15) or anded_a(16) or anded_a(17) or anded_a(18) or anded_a(19) or anded_a(20) or anded_a(21) or anded_a(22) or anded_a(23) or anded_a(24) or anded_a(25) or anded_a(26) or anded_a(27) or anded_a(28) or anded_a(29) or anded_a(30); output1 <= anded_b(0) or anded_b(1) or anded_b(2) or anded_b(3) or anded_b(4) or anded_b(5) or anded_b(6) or anded_b(7) or anded_b(8) or anded_b(9) or anded_b(10) or anded_b(11) or anded_b(12) or anded_b(13) or anded_b(14) or anded_b(15) or anded_b(16) or anded_b(17) or anded_b(18) or anded_b(19) or anded_b(20) or anded_b(21) or anded_b(22) or anded_b(23) or anded_b(24) or anded_b(25) or anded_b(26) or anded_b(27) or anded_b(28) or anded_b(29) or anded_b(30); end process; end Behavioral;  

 

and this component 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity address_decode is port( address : in std_logic_vector(4 downto 0); wr : in std_logic; sw : out std_logic_vector(30 downto 0) ); end entity; architecture arch1 of address_decode is signal a,b,c,d,e : std_logic; begin a <= address(4); b <= address(3); c <= address(2); d <= address(1); e <= address(0); sw(0) <= not a and not b and not c and not d and e and wr; --00001 sw(1) <= not a and not b and not c and d and not e and wr; --00010 sw(2) <= not a and not b and not c and d and e and wr; --00011 sw(3) <= not a and not b and c and not d and not e and wr; --00100 sw(4) <= not a and not b and c and not d and e and wr; --00101 sw(5) <= not a and not b and c and d and not e and wr; --00110 sw(6) <= not a and not b and c and d and e and wr; --00111 sw(7) <= not a and not b and not c and not d and e and wr; --01000 sw(8) <= not a and b and not c and not d and not e and wr; --01001 sw(9) <= not a and b and not c and d and not e and wr; --01010 sw(10) <= not a and b and not c and d and e and wr; --01011 sw(11) <= not a and b and c and not d and not e and wr; --01100 sw(12) <= not a and b and c and not d and e and wr; --01101 sw(13) <= not a and b and not c and d and e and wr; --01110 sw(14) <= not a and b and c and d and e and wr; --01111 sw(15) <= a and not b and not c and not d and not e and wr;--10000 sw(16) <= a and not b and not c and not d and e and wr; --10001 sw(17) <= a and not b and not c and d and not e and wr; --10010 sw(18) <= a and not b and not c and d and e and wr; --10011 sw(19) <= a and not b and c and not d and not e and wr; --10100 sw(20) <= a and not b and c and not d and e and wr; --10101 sw(21) <= a and not b and c and d and not e and wr; --10110 sw(22) <= a and not b and c and d and e and wr; --10111 sw(23) <= a and b and not c and not d and not e and wr; --11000 sw(24) <= a and b and not c and not d and e and wr; --11001 sw(25) <= a and b and not c and d and not e and wr; --11010 sw(26) <= a and b and not c and d and e and wr; --11011 sw(27) <= a and b and c and not d and not e and wr; --11100 sw(28) <= a and b and c and not d and e and wr; --11101 sw(29) <= a and b and c and d and not e and wr; --11110 sw(30) <= a and b and c and d and e and wr; --11111 end arch1;  

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I am trying it out now.
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TO_BE_DONE

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