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Output for only one clock cycle

Altera_Forum
Honored Contributor II
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Hi all, 

 

I have a counter that counts up every time an input of '1' is seen. At the max count value a flag should output '1' and the count resets. I can achieve this, however the output lasts for as long as the input stays at '1' on the final count. 

 

How do you code for an output to last for just one clock cycle? 

 

Thanks
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Altera_Forum
Honored Contributor II
723 Views

 

--- Quote Start ---  

Hi all, 

 

I have a counter that counts up every time an input of '1' is seen. At the max count value a flag should output '1' and the count resets. I can achieve this, however the output lasts for as long as the input stays at '1' on the final count. 

 

How do you code for an output to last for just one clock cycle? 

 

Thanks 

--- Quote End ---  

 

 

my guess. you haven't put else statement or default value for that output. where is your code.
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Altera_Forum
Honored Contributor II
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I'm in work and its on my laptop, let me type it over.

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Altera_Forum
Honored Contributor II
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here: 

 

process 

begin 

if reset = '1' then count <= 0; 

elsif rising_edge (clk) then  

if count < 255 then 

if input = '1' then count <= count + 1; 

end if; 

end if; 

end;
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Altera_Forum
Honored Contributor II
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you are asking your count to stay at 255 once it reaches there and where is the output?

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Altera_Forum
Honored Contributor II
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sorry, second process is: 

 

process begin 

if count = 255 then flag <= '1'; 

else flag = '0'; 

end if; 

end;
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Altera_Forum
Honored Contributor II
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well comment out that if count < 255 and its fellow end if. then if your counter is 8 bits it will move back to zero by itself on enable (or on reset)

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Altera_Forum
Honored Contributor II
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Thanks, I removed that, it made no difference to the simulation at all. When input stays '1' the output changes every +ve clk edge. I need the output to only change once for each time the input goes '1', then change again when the input next goes '1' again (after it has been '0').

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Altera_Forum
Honored Contributor II
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now your requirement changed. You want input 0=>1 to enable count and not just 1 so you need to redesign your counter on that basis. 

 

inside process: 

input_d <= input; 

if input = '1' and input_d = '0' then 

count <= count + 1; 

...
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Altera_Forum
Honored Contributor II
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Cheers, 

 

got to get back to work but i'll give it a shot later and get back to you.
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Altera_Forum
Honored Contributor II
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Couldn't get this to work, heres my code in full. Sorry if I confused the question. What happens is that whenever on_input = '1' then the count increases every time the clk goes +ve. I require it to count up only once no mater how long the on_input is held at '1'. I can see why the design I have operates as it does, but I can't work out how to change it to what I need. I need the overflow to act in a similar way. Thanks. 

 

 

entity counter is 

port (clk : in std_logic; 

on_input : in std_logic; 

reset : in std_logic; 

overflow : out std_logic; 

values : out integer range 0 to 255); 

end counter; 

 

architecture Behavioral of counter is 

 

signal count : integer range 0 to 255;  

 

begin 

 

counter_process : process (clk, reset, on_input) 

 

begin 

if reset = '1' then count <= 0; 

elsif rising_edge (clk) and on_input = '1' then  

if count < 255 then 

count <= count + 1;  

end if; 

else count <= count;  

end if;  

 

 

end process counter_process; 

 

overflow_process : process (count) 

begin 

if count > 255 then overflow <= '1'; 

else overflow <= '0'; 

end if; 

end process overflow_process; 

 

values <= count; 

 

end Behavioral;
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Altera_Forum
Honored Contributor II
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you wanted count to go from 0 to 255 and back, yet you are asking if count > 255 which will never occur in your new code. 

 

Here is code for my understanding of your plans earlier in your post 

 

entity counter is port (clk : in std_logic; on_input : in std_logic; reset : in std_logic; overflow : out std_logic; values : out integer range 0 to 255); end counter; architecture Behavioral of counter is signal count : integer range 0 to 255; signal on_input_d: std_logic := '0'; begin process (clk, reset) begin if reset = '1' then count <= 0; on_input_d <= '0'; elsif rising_edge (clk) then on_input_d <= on_input; if on_input = '1' and on_input_d = '0' then count <= count + 1; end if; end if; end process; process (count) begin if count = 255 then overflow <= '1'; else overflow <= '0'; end if; end process; values <= count; end Behavioral;
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Altera_Forum
Honored Contributor II
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Hey! Thanks for that it worked a treat! And I understand how it works. A real help, thank you!

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