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17268 Discussions

PCIE Qsys design flow issue

Altera_Forum
Honored Contributor II
‎10-17-2014 07:38 AM
1,085 Views

Hi Dears, 

 

I design pice project according user guide, when i set parameters of pcie as UG i will get a error as below: 

"Error: pcie_hard_ip_0.pcie_internal_hip: Stratix IV GX and Arria II GZ do not support a non-maximum RX buffer credit allocation" 

 

So i can only change the setting to "Maximum" as attached file shows. 

 

 

Could this be only a DOC debug?!
multiple-attachments.zip
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