PCIe Compiler Serdes pll

[Altera_Forum]

Hi! 

 I have a problem with the PCIe Compiler: I add the PCIe IP in my quartus IV project (with the SOPC builder, later with the MegaWizard) and add exernal Pins to "refclk", "rx_in0" and "tx_out0" and start to compile.  The compilation stop with these error messages: Error: PLL "pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0 Error: PLL "pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk1_multiply_by and/or clk1_divide_by are either unspecified or set to 0 Error: PLL "pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk2_multiply_by and/or clk2_divide_by are either unspecified or set to 0 Error: RX PMA element 'pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|receive_pma0' has an illegal SIGNAL_DETECT_LOSS_THRESHOLD parameter setting of 1 Info: "3" is a legal value Error: RX PMA element 'pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|receive_pma0' has an illegal SIGNAL_DETECT_HYSTERESIS_VALID_THRESHOLD parameter setting of 1 Info: "14" is a legal value Error: RX PMA element 'pcie:inst|pcie_serdes:serdes|pcie_serdes_alt_c3gxb_sdb8:pcie_serdes_alt_c3gxb_sdb8_component|receive_pma0' has an illegal SIGNAL_DETECT_HYSTERESIS parameter setting of 3 Info: "4" is a legal value When i double click on the three first messages i see this code: UNCTION cycloneiv_pll (areset, clkswitch, configupdate, fbin, inclk, pfdena, phasecounterselect, phasestep, phaseupdown, scanclk, scanclkena, scandata) WITH ( AUTO_SETTINGS, BANDWIDTH, BANDWIDTH_TYPE, C0_HIGH, C0_INITIAL, C0_LOW, C0_MODE, C0_PH, C0_TEST_SOURCE, C1_HIGH, C1_INITIAL, C1_LOW, C1_MODE, C1_PH, C1_TEST_SOURCE, C1_USE_CASC_IN, C2_HIGH, C2_INITIAL, C2_LOW, C2_MODE, C2_PH, C2_TEST_SOURCE, C2_USE_CASC_IN, C3_HIGH, C3_INITIAL, C3_LOW, C3_MODE, C3_PH, C3_TEST_SOURCE, C3_USE_CASC_IN, C4_HIGH, C4_INITIAL, C4_LOW, C4_MODE, C4_PH, C4_TEST_SOURCE, C4_USE_CASC_IN, CHARGE_PUMP_CURRENT, CHARGE_PUMP_CURRENT_BITS, CLK0_COUNTER, CLK0_DIVIDE_BY, CLK0_DUTY_CYCLE, CLK0_MULTIPLY_BY, CLK0_OUTPUT_FREQUENCY, CLK0_PHASE_SHIFT, CLK0_PHASE_SHIFT_NUM, clk0_use_even_counter_mode, clk0_use_even_counter_value, CLK1_COUNTER, CLK1_DIVIDE_BY, CLK1_DUTY_CYCLE, CLK1_MULTIPLY_BY, CLK1_OUTPUT_FREQUENCY, CLK1_PHASE_SHIFT, CLK1_PHASE_SHIFT_NUM, clk1_use_even_counter_mode, clk1_use_even_counter_value, CLK2_COUNTER, CLK2_DIVIDE_BY, CLK2_DUTY_CYCLE, CLK2_MULTIPLY_BY, CLK2_OUTPUT_FREQUENCY, CLK2_PHASE_SHIFT, CLK2_PHASE_SHIFT_NUM, clk2_use_even_counter_mode, clk2_use_even_counter_value, CLK3_COUNTER, CLK3_DIVIDE_BY, CLK3_DUTY_CYCLE, CLK3_MULTIPLY_BY, CLK3_OUTPUT_FREQUENCY, CLK3_PHASE_SHIFT, CLK3_PHASE_SHIFT_NUM, clk3_use_even_counter_mode, clk3_use_even_counter_value, CLK4_COUNTER, CLK4_DIVIDE_BY, CLK4_DUTY_CYCLE, CLK4_MULTIPLY_BY, CLK4_OUTPUT_FREQUENCY, CLK4_PHASE_SHIFT, CLK4_PHASE_SHIFT_NUM, clk4_use_even_counter_mode, clk4_use_even_counter_value, CLKOUT_WIDTH = 5, COMPENSATE_CLOCK, DPA_DIVIDE_BY, DPA_MULTIPLY_BY, ENABLE_SWITCH_OVER_COUNTER, INCLK0_INPUT_FREQUENCY, INCLK1_INPUT_FREQUENCY, LOCK_HIGH, LOCK_LOW, lock_window_ui, lock_window_ui_bits, LOOP_FILTER_C, LOOP_FILTER_C_BITS, LOOP_FILTER_R, LOOP_FILTER_R_BITS, M, M_INITIAL, M_PH, M_TEST_SOURCE, N, OPERATION_MODE, PFD_MAX, PFD_MIN, PHASECOUNTERSELECT_WIDTH = 3, PLL_COMPENSATION_DELAY, PLL_TYPE, SCAN_CHAIN_MIF_FILE, self_reset_on_loss_lock, SIMULATION_TYPE, SWITCH_OVER_COUNTER, SWITCH_OVER_TYPE, TEST_BYPASS_LOCK_DETECT, USE_DC_COUPLING, VCO_CENTER, VCO_DIVIDE_BY, vco_frequency_control, VCO_MAX, VCO_MIN, VCO_MULTIPLY_BY, vco_phase_shift_step, VCO_POST_SCALE, VCO_RANGE_DETECTOR_HIGH_BITS, VCO_RANGE_DETECTOR_LOW_BITS) RETURNS ( activeclock, clk, clkbad, fbout, fref, icdrclk, locked, phasedone, scandataout, scandone, vcooverrange, vcounderrange); --synthesis_resources = cycloneiv_pll 1 SUBDESIGN altpll_ld81 ( areset : input; clk : output; fref : output; icdrclk : output; inclk : input; locked : output; ) VARIABLE pll1 : cycloneiv_pll WITH ( BANDWIDTH_TYPE = "auto", CLK0_DIVIDE_BY = 0, CLK0_MULTIPLY_BY = 0, CLK1_DIVIDE_BY = 0, CLK1_MULTIPLY_BY = 0, CLK2_DIVIDE_BY = 0, CLK2_DUTY_CYCLE = 20, CLK2_MULTIPLY_BY = 0, DPA_DIVIDE_BY = 0, DPA_MULTIPLY_BY = 0, INCLK0_INPUT_FREQUENCY = 10000, OPERATION_MODE = "no_compensation" ); BEGIN pll1.areset = areset; pll1.fbin = pll1.fbout; pll1.inclk = inclk; clk = ( B"0", pll1.clk); fref = pll1.fref; icdrclk = pll1.icdrclk; locked = pll1.locked; END;The clocks divider and multipyer get initialized with zero, when i change it to 1, the compilation get successful! So i think something with the configuration of the internal pll goes wrong. When i instance the ip in my toplevel block diagramm and i add no pin the compiltion get successful!  Is there someting special to setup for the pcie ip?  Thank you!

[Altera_Forum]

I still have the problem, no idea?

[Altera_Forum]

I have the same issue. Changed it manually to the same parameters the High Performance DMA example uses ... (as i'm trying the chaining DMA example) 

Although i don't know if this is the correct way to solve the problem ...

[Altera_Forum]

Hi! 

Thank you for the tip, but when i compile the example (chaining_dma) i get the same errors: Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0 Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk1_multiply_by and/or clk1_divide_by are either unspecified or set to 0 Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk2_multiply_by and/or clk2_divide_by are either unspecified or set to 0 Can you post your settings?

[Altera_Forum]

You'll have to alter two files :  

 <variation>_serdes.vhd    ... signal_detect_hysteresis => 4, signal_detect_hysteresis_valid_threshold => 14, signal_detect_loss_threshold => 3, ...   <variation>_examples\chaining_dma\db\altpll_sc81.tdf   ... VARIABLE pll1 : cycloneiv_pll WITH ( BANDWIDTH_TYPE = "high", CLK0_DIVIDE_BY = 2, CLK0_MULTIPLY_BY = 25, CLK1_DIVIDE_BY = 10, CLK1_MULTIPLY_BY = 25, CLK2_DIVIDE_BY = 10, CLK2_DUTY_CYCLE = 20, CLK2_MULTIPLY_BY = 25, DPA_DIVIDE_BY = 2, DPA_MULTIPLY_BY = 25, INCLK0_INPUT_FREQUENCY = 10000, OPERATION_MODE = "no_compensation" ); ...  Let me know if this is working. Normally it should compile and synthesize now. Bust when you'll run the generated chaining_dma testbench in ModelSim it will run but you'll get messages telling you again : CLK0_DIVIDE_BY should be more then '0'.   I'm not really sure if it's a 100 % solution ...

[Altera_Forum]

Hi! 

Last month i hand no time to test... I changed the pll settings and quartus compile without errors, but atm i have no hardware to check. I let you know when i testet it with hardware!  Is this a quartus bug? Is there a buglist from quartus?

[Altera_Forum]

I think this issue is related to the supported devices. If you didn't install support for all devices, you may sometimes get this error. I had this same error and had to reinstall Quartus 10.1 SP1. I am now verifying that this fixes the issue and will report back once it is tested. 

 Check this link for more information : http://www.altera.com/support/kdb/solutions/rd02102011_218.html