PCIe EP BAR0 size mismatch between Configuration value and FPGA value

[SivaKona]

Hi,

I have Generated "Intel L-/H-Tile Avalon memory mapped for PCI Express" IP in PIO with BAR0 size set to 36 bits (64 G Bytes)

On FPGA HW Platform, The EP BAR0 size appears to be 8 bits only,.
What could be the reason for this behavior?

Tool Version : Quartus Prime Version 21.2.0 Build 72 06/14/2021 SC Pro Edition

Regards

Siva Kona

[SivaKona]

Hi,

The ep_altera_pcie_s10_hip_avmm_bridge_2211 bridge parameters are not getting set as per the configuration in GUI 

pcie_g3x8_ep_altera_pcie_s10_hip_avmm_bridge_2211_enrjqki #(
.enable_rx_buffer_limit_ports_hwtcl (1),
.pf0_bar0_address_width_hwtcl (7),  // Was set in 36 bits
.pf0_bar0_enable_rxm_burst_hwtcl (1),
.pf0_bar1_address_width_hwtcl (0),
.pf0_bar1_enable_rxm_burst_hwtcl (0),
.pf0_bar2_address_width_hwtcl (0),
.pf0_bar2_enable_rxm_burst_hwtcl (0),
.pf0_bar3_address_width_hwtcl (0),
.pf0_bar3_enable_rxm_burst_hwtcl (0),
.pf0_bar4_address_width_hwtcl (7),  // Was set in 9 bits
.pf0_bar4_enable_rxm_burst_hwtcl (0),
.pf0_bar5_address_width_hwtcl (0),
.pf0_bar5_enable_rxm_burst_hwtcl (0),
.pf0_expansion_base_address_register_hwtcl (0),

Need help!

Regards

Siva Kona

[SivaKona · Accepted solution]

Hi,

By default the bar0_address_widths are set to 7.

In standalone IP generation steps, The IP instance parameter value is not changing as per selected BAR0 Size. 

But when PCIe EndPpoint is generated as part of complete System design along with other components, a component instance Warning showed up sighting the mismatch in instance address width value and component address width value .

Sync-ing both these address widths as per design Arch, fixed the issue.

How can we control instance parameter while generating Standalone IP (Intel L/H Tile Avalon Memory Mapped for PCI Express)?

Regards

Siva Kona