PCIe hard IP BAR to On-chip memory addressing

[Markgel]

using Cyclone IV hard ip and On-chip memory 32B mapped to 0x-0x1F 

BAR0 mapped to 0xA1200000-0xA0001F

Reading BAR0 at offset 0 should have access first byte of On-chip memory? Reading 0xff instead of memory content.

[JohnT_Intel]

Hi,

Could you share with me your Quartus design? How do you confirm that you are reading the correct addressing? Have you try to use SignalTap to tap the on chip memory IP interface?

[Markgel]

Attached the design.  Regarding the addressing - trying to read and write to BAR0, but can't catch any activity for On chip memory signals using the SignalTap.

[JohnT_Intel]

Hi,

From your design, I observed that you are not using the correct clock on the on chip memory. The clock should be from the PCIe Clock output so that the clock is sync between Bar 0 and On Chip Memory.

Please refer to https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/an-456-pci-express-high-performance-reference-design-for-cyclone-iv-gx-fpga/ for the design example.

[Markgel]

tried to implement design suggested (attached), but still reading 0xFF from the BARs memory:

[JohnT_Intel · Accepted solution]

Hi,

May I know if you enable the PCIe BAR0? Have you try to performed SignalTap?

[Markgel]

Hi

  Yes, indeed was a problem that win driver blocked the BAR0. Thanks for support.

BR,

Mark.

[JohnT_Intel]

Hi,

May I know if the issue is resolved after you unblock the BAR0?

[Markgel]

Yes, it does - can access to the BARs memory.

[JohnT_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.