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Hi,
I am trying to use the SFP+ connectors from the 10G BASE-R megafunction on a Stratix V FPGA. I just want to connect the two SFP+ ports with a external cable and do BER testing on the system. However, when I try to compile the design with the PHY IP core, I get the error: Error: Peak virtual memory: 844 megabytes Can anyone help me with debugging this? ThanksLink Copied
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Enlarge your page file size on Windows.
Use a PC with a higher performance, specially more RAM.
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