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Altera_Forum
Honored Contributor I
870 Views

PI loop filter logic in Verilog

Hello, the attached photo with the verilog code is taken from the attached article. 

There are two variables, integral and proportional when clk=1 thenintegral decreases ,when clk=0 then it decreases.Proportional toggles from negative to positive with the FILT amplitude.and both of them goes into vtcl with is the factor controlling the period of the VCO.how this logic represnt PID loop filter?Thanks
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3 Replies
Altera_Forum
Honored Contributor I
74 Views

Your input is the phase error (either + or -) 

The PI filter is just an accumultor of this error : accum <= accum + error (the result can lso be divided as a fraction=leaky accumulator) 

The Proportional term is just part of error sample added to accum, How much P is added is up to testing 

 

Note that you are mistaken about clock edge. The error is either + or - tested on same clock edge
Altera_Forum
Honored Contributor I
74 Views

Hello, i am trying to build a test bench for a PI conntroller based on the attached article. 

 

whole code is playing with coefficient for the last line. 

how do you recooment to represent the coefficients in the testbench? 

 

Thanks 

[VHDL] 

always# ((t0-vctl*kphi)/2) vco<=~vco; 

[/VHDL] 

 

 

[VHDL] 

module loop_filter(t0,clk,integral,proportional,filt_i,filt_p,vtcl,kptl,vtcl,vco); 

 

input t0,smpclk,integral,proportional,filt_i,filt_p,vtcl,kptl,vtcl; 

output vco; 

 

reg integral=4'b0; 

reg proportional=4'b0; 

 

always @(posedge smpclk) 

begin 

if (pdup==1'b1) begin 

integral=integral+filt_i; 

proportional=filt_p; 

end 

else if (pdup==1'b0) 

begin 

integral=integral-filt_i;  

proportional=-filt_p; 

end 

else begin 

proportional=0; 

end 

 

always# ((t0-vctl*kphi)/2) vco<=~vco; 

end 

endmodule 

[/VHDL]
Altera_Forum
Honored Contributor I
74 Views

You should not follow that paper as it seems to me it is out of date and the author doesn't seem to know that you can use signed values instead of "pdup" logic. He assumed magnitude then applying for difference sense in logic. 

 

For proper PLL you need to design a frequency generator inside your rtl. Then input another close frequency that you can vary its frequency or phase slightly. You compare the two frequencies (input and reference) and you may add dividers as well if you want more advanced PLL. The comparator will output the signed value of difference which you take to the integral and accumulator directly without the logic proposed in that paper. Then apply filtered output on the input frequency phase.