I need to implement parallel-to-serial and serial-to-parallel blocks. Is there any megawizard/function that does this in the Quartus? and if not, how can I do it efficiently using verilog? Thank you.
you can use the LPM_SHIFTREG Megafunction or elementary HDL contsructs like this always @(posedge clk)
begin
sr <= { sr, si}; // left shift, serial input
end Regards, Frank
