PLL Lock time in post synth sim

[Altera_Forum]

Does any one how much simulation is required for a pll to lock in a gate level post synthesis simulation? 

 Input clock is 100MHz, output clock is $125MHz.  Modelsim prints this message   Note : StratixIII PLL was reset # Time: 8464 Instance: tbgate_a_q.GateA_inst.\sys_pll|altpll_component|auto_generated|pll1   I ran to 100us and lock is still not asserted. i will try 1ms.

[Altera_Forum]

If I remember correctly, simulation tools can't tell the actual lock time. Lock time might be affect by adjacent noise or the quality of the input clock which able to model by simulation tools.