Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15548 Discussions

PLL Simulation not working fine

Altera_Forum
Honored Contributor II
1,107 Views

Hello, 

I am using Quartus Prime 17.0 version. In that when I am using PLL IP for clock generation, then during simulation I am not getting continuous clock at the output rather getting continous clock for some cycles and then a sudden high or low and after some input clock cycles again it gets continous, same sequence is followed again and again. Please it would be great if anyone would help me with this.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
136 Views

what is the status of the locked signal? could be that the PLL has not locked yet. 

 

Otherwise, is there a real need to simulate the PLL in your testbench? It can often take a long time to lock and can be rather slow. If your UUT is something other than PLL, its usually easier just to generate the clocks in the testbench.
Altera_Forum
Honored Contributor II
136 Views

Hello, 

Thanks for the answer but locked signal is working fine. Its like I am getting the required frequency at the output, but the clock generated, is not continuous. And yes there is requirement to use PLL.
Altera_Forum
Honored Contributor II
136 Views

Check the timescale you are using and frequency for input reference clock of PLL.. 

 

Share a screenshot of Waveform..
Reply