PLL inclock legal source reported as illegal

[Altera_Forum]

==622MHz==> FAST_PLL0 ==77MHz==>| 

==622MHz==> FAST_PLL1 ==77MHz==>| CLK_CTRL ==77MHz==> ENH_PLL  This is basically my setup, the select signal to the CLK_CTRL block depends on which FAST_PLL that has locked. I get this error during compilation: Error: Clock input port inclk of PLL "pll_enh:pll_enh_i|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info: Input port INCLK of node "pll_enh:pll_enh_i|altpll:altpll_component|pll" is driven by clkctrl:clkctrl_i|clkctrl_altclkctrl_6ke:clkctrl_altclkctrl_6ke_component|outclk which is COMBOUT output port of Combinational cell type node clkctrl:clkctrl_i|clkctrl_altclkctrl_6ke:clkctrl_altclkctrl_6ke_component|outclk  Any ideas?

[Altera_Forum]

Just removed option "ensure glitch-free operation" from CLK_CTRL settings seeing as the inserted registers make it a non-direct connection between PLL and CLK_CTRL. This however, generated a new error: 

Error: Port outclk of Clock Control Block "singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3" can't drive inclk port of Clock Control Block "clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1" Error: Can't merge Clock Control Blocks singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3 and clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1 -- singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3 feeds logic that is not clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1This PLL chaining is driving me nuts. Is there really no way to implement my design?