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PLL input clock inclk[0] is not f ully compensated because it is fed by a remote clock pin

Diego2
Novice
187 Views

Hello

I have a design for a Cyclone 10 LP FPGA with a PLL that is fed from a clock-dedicated pin. The PLL was generated in "Normal Mode", however I'm getting this Critical Warning

Critical Warning (176598): PLL "..." input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_M1" File: ...

I'm not 100% familiar with the clock architectures of Intel devices. Can someone explain me what this means? Am I not suppose to use this mode when using an external pin as a clock input?

Thanks!

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1 Solution
Ash_R_Intel
Employee
177 Views

Hi Diego,


Please refer Figure 38 of Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...)


Each PLL has dedicated input pins, indicated by a solid line and dotted line. The solid line are the dedicated pins for that particular PLL. For example, PLL_1 has CLK[3:0]. However, PLL_1 can also be driven by other dedicated pins CLK[15:12}, but they are not associated ones for PLL_1.


Refer statement in section 4.2.4 "Input and output delays are fully compensated by the PLL only if you are using the

dedicated clock input pins associated with a given PLL as the clock sources."


To avoid the warning, use associated dedicated pins for the PLL.


Regards


View solution in original post

2 Replies
Ash_R_Intel
Employee
178 Views

Hi Diego,


Please refer Figure 38 of Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...)


Each PLL has dedicated input pins, indicated by a solid line and dotted line. The solid line are the dedicated pins for that particular PLL. For example, PLL_1 has CLK[3:0]. However, PLL_1 can also be driven by other dedicated pins CLK[15:12}, but they are not associated ones for PLL_1.


Refer statement in section 4.2.4 "Input and output delays are fully compensated by the PLL only if you are using the

dedicated clock input pins associated with a given PLL as the clock sources."


To avoid the warning, use associated dedicated pins for the PLL.


Regards


View solution in original post

Diego2
Novice
164 Views

Thanks for the response! That was what I was looking for.

Reply