PLL output pins question

[adamShiau]

Hi everyone,

I have a Cyclone IV (EP4CE15F17) FPGA board that uses a 50MHz clock input fed to a PLL. It then generates three clocks for ADC、DAC and SDRAM。  

The clock pin assignment is as below , and it works well.

But when I read the following lines from the Device Handbook, I become confused: 

External Clock Outputs

"Each PLL of Cyclone IV devices supports one single-ended clock output or one differential clock output. Only the C0 output counter can feed the dedicated external clock outputs, as shown in Figure 5–11, without going through the GCLK. Other output counters can feed other I/O pins through the GCLK."

My questions:

1. I'm using a single PLL and generating three single-ended clocks, which doesn't align with the statement "Each PLL of Cyclone IV devices supports one single-ended clock output."

2.  From the compilation report, I'm using PLL_2 (shown in the pictures below)，

c[0] is connects to PLL_DAC_CLK with pin function "PLL4_CLKOUTn",

c[1] is connects to PLL_SDRAM_CLK with pin function "PLL2_CLKOUTn",

c[2] is connects to CPU_CLK which is to Nios CPU，

c[3] is connects to PLL_ADC_CLK with pin function "PLL2_CLKOUTp",

Is my connection correct? Because according to Figures 5-11, only C[0] can be connected to PLL#_CLKOUT(p, n). Then why does it still function properly when I make this connection?

Adam.S

[FvM]

Hi,
the difference is between dedicated clock output and I/O pin fed through global clock network. According to the quoted device handbook information, all three outputs are non-dedicated clock outputs. They involve higher jitter and delay skew than dedicated outputs but most likely will work well for your application.

[adamShiau]

Hi FvM,

Thank you for the response.

In my case, if I want to generate three dedicated clock outputs to an external device using only one clock input, do I need to physically connect the input clock pin to three PLL inputs (via PCB trace) and assign the PLL#_CLKOUT of each PLL to PLL output counter C[0]?

Alternatively, can I internally connect PLL output counters other than PLL C[0] to inputs of other PLL instances (via FPGA interconnection fabric) and then derive C[0] as an external clock output?"

Adam.S

[FvM · Accepted solution]

Hi,
sure you need dedicated clock outputs for all three clocks?

If so, separate PLLs are required each output. Input to the PLLs can be provided in different ways. If performance of the clock outputs is as critical as you assume, they should be probably fed by direct clock inputs. Propagating the reference clock through clock network will also involve jitter and delay skew.

It would be however better to rote a single reference clock input to all PLLs than cascading PLLs.