I'm having problems with a small part of a pretty big design. I want to phase shift a PLL output (Stratix II) and have instantiated megafunctions for PLL and PLL_RECONFIG and connected them like this:
// ========================================================================
// Signals
// ========================================================================
wire scanclk, scandata, scanread, scanwrite, scandataout, scandone;
wire reconf_busy, reconf_reset;
wire pll_areset;
wire data_in;
// ========================================================================
// PLL_RX
// ========================================================================
ext_pll_rx pll_rx_i ( .areset ( pll_areset ),
.inclk0 ( hs_rx_clk ),
.scanclk ( scanclk ),
.scandata ( scandata ),
.scanread ( scanread ),
.scanwrite ( scanwrite ),
.c0 ( c0 ),
.locked ( locked ),
.scandataout ( scandataout ),
.scandone ( scandone ),
.enable0 ( enable ),
.sclkout0 ( sclkout ) );
// ========================================================================
// PLL_RX Reconfig
// ========================================================================
pll_rx_reconfig pll_rx_reconfig_i ( .clock ( clk ),
.counter_param ( 3'b010 ),
.counter_type ( 4'b0100 ),
.data_in ( data_in ),
.pll_areset_in ( 1'b0 ),
.pll_scandataout ( scandataout ),
.pll_scandone ( scandone ),
.read_param ( 1'b0 ),
.reconfig ( phase_shift ),
.reset ( reconf_reset ),
.write_param ( write_param ),
.busy ( reconf_busy ),
.data_out ( ),
.pll_areset ( pll_areset ),
.pll_scanclk ( scanclk ),
.pll_scandata ( scandata ),
.pll_scanread ( scanread ),
.pll_scanwrite ( scanwrite ) );But during Analysis & Synthesis I receive the following warning: Warning: PLL "singlechannel:ch0_i|pll_rx_ps:pll_rx_ps_i|ext_pll_rx:pll_rx_i|altpll:altpll_component|pll" has scan reconfiguration ports connected, but PLL scan reconfiguration is not being used (since port SCANDATA is not connected)
Warning: PLL "singlechannel:ch0_i|pll_rx_ps:pll_rx_ps_i|ext_pll_rx:pll_rx_i|altpll:altpll_component|pll" has port SCANCLK connected when PLL scan reconfiguration is not being usedI also get this: Warning (14320): Synthesized away node "singlechannel:ch0_i|pll_rx_ps:pll_rx_ps_i|pll_rx_reconfig:pll_rx_reconfig_i|pll_rx_reconfig_pllrcfg_j0r:pll_rx_reconfig_pllrcfg_j0r_component|altsyncram:altsyncram3|altsyncram_f2r:auto_generated|q_a"Why would it not accept my connections? I've spent quite some time on this now and am getting pretty frustrated. Would be very thankful for any help on the matter!
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I found it, not sure which of the following measures that fixed it though:
Proper reset of altpll_reconfig (old one didn't need this) Have a scan chain memory initialization file for the altpll_reconfig block Slowed down reconfiguration clock from 20 MHz to ~1MHz