Parallel Flash Loader with CFI Flash error "Can't recognize silicon ID for device 2"

[Altera_Forum]

Hi Everyone! First time asking a question. I am having an issue that is making me crazy! Please help if you can. 

 I copied configuration portions of the Stratix V SigInt Eval board into my custom board. I have a Stratix V FPGA as the first device in the JTAG chain and a MAX II CPLD system controller as the second device in the chain. There is a CFI_1Gb FLASH connected to both the CPLD and FPGA as shown in the Eval board. That is my basic setup. I am using both the 11.x tools and the beta 12.0 tools for Stratix V.   I am using the MegaWizard PFL IP as FLASH programmer only and put it in a CPLD design. Only other code in the CPLD is a LED blinker. I have checked and re-checked that the pin out is right on everything. The FPGA is unprogrammed (although I have tried with it programmed too). I am using the Quartus programmer and the USB Blaster to see the JTAG Chain. I can configure the FPGA and program the CPLD. I add the CFI-1Gb FLASH to the CPLD. When trying to program the converted .POF file into the FLASH, I get the following error every time! I have tried what seems to be a million times and each time the same error!   Error: "Can't recognize silicon ID for device 2"   I then put the PFL design in the FPGA and erased the CPLD, same error except that the device number changed.    Error: "Can't recognize silicon ID for device 1"   I then instantiated SignalTap into the FPGA. I can see that the PFL IP is doing something, but I could not capture enough traces to see what is wrong.    I have changed the modes on MSEL pins, but this makes no sense to me. No luck.   Finally, I have found the TopJTAG Boundary Scan Programmer tool online. I have used it and able to see the FLASH and it reports the type, size, etc. I am trying to program the FLASH with it now, but it is VERY slow and has been running for two days. This will maybe get me over a hump, but is not a long term solution.    I have searched this forum, Google, and others for hours looking for solutions. The Webcase support sucks! They are absolutely no help. No answer. In my searches, I found some references to this and verified the few that I found, but I have not corrected my problem.   Can anyone help me? I am an experienced Xilinx FPGA guy, but new to the Altera side and am struggling.    I also know about the NIOS programmer, but being new to Altera, I did not want to bite that off yet either. I have never used NIOS. The PFL IP seems simple enough, but I cannot get this thing to work.    I really appreciate any help you can give.   Thanks! Cameron

[Altera_Forum]

I am having the exact same problem. Did you ever find a solution to this issue?

[Altera_Forum]

No solution for the exact error. However, I did confirm with the factory that in using the PFL IP utility and generating VHDL, it would not work correctly. I used the PFL IP utility and generated a schematic block and got it working. Seems to be a bug in code generation. I moved on. Sorry I am no help. Maybe someday someone will find an answer to this. I have seen that many have had the same problem.

[Altera_Forum]

Thanks for the reply. My issue turned out to be a dumb user error... I had the flash_data pins as outputs rather than bidirectional IO. I don't know how I missed that, but, once corrected it worked like a charm.

[Altera_Forum]

Hi, 

 I am currently working on a similar project and have the same problem. My board consists of a MAX2 EPM570T100 connected to a 16Mbit CFI Flash Nymonyx M29W160ET. I created the PFL Instances in several ways with the wizard. But no matter which output files are created, the synthesis works without errors. But after succesful programm and verify the flash is not recognized. I already defined the IC in the dialog. When I use the "Auto Detect" feature of the programmer, i get an "Unexpected error in JTAG server -- error code 1" after a few seconds. If I add the flash to the clpd by hand, i experience the same problem like the initial poster. The silicon ID cannot be recognized and the operation fails. Is there a certain version of quartus that i have to use, to get it working? I am currently using 12.0sp2 because of the interoperability with other design software. The created qip file is set as top level design.  I hope somebody can help me to find a solution for this.  Thanks! Alexander

[Altera_Forum]

Hi Alexander, 

 The first thing to verify is that all of the IO related to the flash device are configured correctly and properly connected to the PFL implementation in your design. Even if there are errors here it will likely synthesize correctly, however, the communication with the flash device won't work. That was my experience and as soon as it was corrected everything worked fine. Mine was implemented as a schematic block, but, Cameron had issues with the generated code so use your PFL design is a schematic block rather than VHDL or Verilog instantiation, if it's not already.  I hope this helps and you can find a solution to your problem.