Internal Error with EDA Netlist Writer

[Altera_Forum]

Dear People 

 I have this error when I run EDA Netlist Writer, once it reaches 25% execution, it says this error    Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_port.cpp, Line: 329 m_port_info.num_of_dimensions() == 1 Stack Trace:  0x25c74: WSC_PORT::bus_member_index + 0x94 (NETO_WSC)  0x9ad3: VHDO_WRITER::write_routing_wire_instances + 0x3a3 (NETO_VHDO)  0x178cc: VHDO_WRITER::write_atom_instances + 0x23c (NETO_VHDO)  0x19c42: VHDO_WRITER::write_module + 0x212 (NETO_VHDO)  0x338c: VHDO_WRITER::write_hierarchy_info + 0xcc (NETO_VHDO)  0x12b42: VHDO_WRITER::write_file + 0x5c2 (NETO_VHDO)        0x117eb: qexe_get_tcl_sub_option + 0x1dbb (comp_qexe)  0x14997: qexe_process_cmdline_arguments + 0x537 (comp_qexe)  0x14aa1: qexe_standard_main + 0xa1 (comp_qexe)   0x1928: msg_exe_fini + 0xf8 (CCL_MSG)  0x18cc: msg_exe_fini + 0x9c (CCL_MSG)  0x57b4: MEM_UTILS_CHUNK_ALLOC::chunk_malloc + 0x194 (ccl_mem)  0x2f084: msg_exe_main + 0x74 (CCL_MSG)  0x2ea29: Eda_pt_Init + 0x2d49 (quartus_eda)  0x1652c: BaseThreadInitThunk + 0xc (kernel32)  0x2c520: RtlUserThreadStart + 0x20 (ntdll)  End-trace  Quartus II 64-Bit Version 11.0 Build 208 07/03/2011 SJ Full Version Service Pack Installed: 1  Can anyone help me with this? I will highly appreciate.  Regards  Waqar, Finland

[Altera_Forum]

Hi Waqar. 

 For internal errors, the best option is always to start a service request with Altera. (log into the my support section of the altera website)  What they will probably ask is an archive of the project (under Project->Archive Project) This will give them your entire design to play with to attempt to reproduce the error.  Once you submit the service request, a thing to try is to delete the DB and Incremental_DB directories from the synthesis directory and try again. Sometimes a corrupt db file will cause issues like this, that just go away when you purge them.  Pete

[Altera_Forum]

Thank you very much pete, I have done as you have said. As a further information, I would say, this error only comes when I declare the ports of my design as virtual pins.

[Altera_Forum]

Can I ask you, is it OK to assign the ports of top level entity as virtual pins except clock? I am doing this because the total number of pins required for the ports of the top level entity are much more than the Stratix IV device family. After this assignment is run the fitter which is successful but once I run the EDA Netlist Writer, after 25%, it gave me that error that I mentioned in the first post.

[Altera_Forum]

I haven't really played with virtual pins, so my guess you are on the correct tract. 

 I would make a new top wrapper that has a smaller number of actual pins and mux the virtual pins into a few real pins so the logic doesn't get optimized out (if you care about them)  And give that a try

[Altera_Forum]

Hi, did you ever file a Service Request for this issue? It would be fantastic for us to get the design to reproduce this IE and fix it for future releases.