Parameterize and/or Infer a FIFO?

[Altera_Forum]

I have a circuit (in VHDL) that uses generics to parameterize the bus width and various other elements of my circuit. I now need to add a FIFO to my datapath and would like that FIFO to utilize the BUS_WIDTH specification from my generic inputs. The way I see it, there should be 2 options: (1) parameterize an Altera-generated FIFO to use my BUS_WIDTH spec, or (2) create my own parameterized FIFO from which Quartus can infer the necessary memory. 

 This seems like it should be really easy to do, but I can't seem to find any documentation on how I can accomplish it. Any help would be much appreciated.  Thanks

[Altera_Forum]

You either write fifo instant in vhdl (as per altera examples...somewhere) or use megawizard to generate a fifo instant, then overwrite its generics by mapping them to your generics.

[Altera_Forum]

Altera has lots of great documentation ... its just that you have to read *all* of it before you find what you are looking for :) 

 For Megafunction FIFOs go read the SCFIFO and DCFIFO user guide;  http://www.altera.com/literature/ug/ug_fifo.pdf  The trick with getting these configured is to use the MegaWizard to generate an instance, and then copy the scfifo or dcfifo component out of the generated .vhd or .v file. That instance will have the generics setup for you using whatever fixed parameters you provided to the MegaWizard, however, once you've copied the format of the component, you can change the fixed parameters back to your generic values.  For 'inferred' FIFOs, I doubt there are any, however, for FIFOs coded using grey codes etc, go read the 'Stratix Cookbook' (its not really specific to Stratix devices);  http://www.altera.com/literature/manual/stx_cookbook.pdf  Cheers, Dave