Re: Parameterized interface modports question

Altera_Forum · ‎07-09-2010

Hi,

I've recently started using SystemVerilog and I wish to use a generic memory interface in some of my modules, in order not to tie their use to a given particular memory or system bus, in a way that I could simply bind adapters to the top of the module hierarchy and let it roll with whatever memory/bus interfaces I wish, with little extra effort.

But the interface is parameterized and contains two modports, as such:

interface GenericMemPort# (parameter int ADDR_WIDTH, DATA_WIDTH);
    logic  addr;
    logic  data;
    logic write, read;
    logic ack;
    
    modport host (input addr, inout data, input write, input read, output ack);
    modport client (output addr, inout data, output write, output read, input ack);
endinterface

Although my particular module hierarchy has tight restrictions as to what size is the address and data bus widths, I would like to keep the interface like that for use in other module hierarchies.

But to do that, I don't understand which syntax to use when using these modports inside modules. How do I define their parameters?

module Raster# (
    parameter int MEM_ADDR_WIDTH = 24 // memory interface address width
)
(
    // clock and reset signals
    input clk,
    input rst,
    
    // memory interface
    ArbiterPort.client
   # (
        .ADDR_WIDTH (MEM_ADDR_WIDTH), // although address width may vary ...
        .DATA_WIDTH (32) // data width HAS to be 32 for this module to work
    ) memory
);
// <todo> module body goes here
endinterface

This doesn't seem to work, and I have seen people saying doing this is impossible. They say you have to generically define "memory" as "interface.client", for example, and set the parameters externally, by first instantiating the interface and tying it to the correct port. But this is a problem, since the module has actual restrictions as to what the data width has to be.

What should I do?

Altera_Forum · ‎07-09-2010

Yeap, AFAIK it is not possible to do like you want.

What seams to be possible is to add an assertion inside the module to test that the address width is 32 and through an error if it doesn't.

But there is a bug in Quartus (acknowledged in version 9.0) that does not let you read the parameters declared in an interface outside of a module :(

Maybe that bug has been fixed in 10.0 ?

Altera_Forum · ‎07-09-2010

I think this is a shame and a language inconsistency (i.e. some language features fail to support or defeat each others' purposes entirely). Should I try VHDL? I just didn't like its syntax much..

In any case, how would you assert an interface parameter value from within a module using it? I thought about using an assert exactly like this, but I thought I should ask other's opinions before, since I've never used assertions and since this particular usage of assertions looks one hell of an ugly hack :p

It'd be easier for me if you could give me a few pointers; I'd be very grateful.

Thanks,

n2

Altera_Forum · ‎07-10-2010

I like VHDL better. The only stuff that SystemVerilog has better than VHDL is the interfaces, but interfaces are limited like you have found out. Mentor Graphics (The company behind Modelsim) wrote a white paper complaining that interfaces are actually evil. I would present a link here, but I can not find it right now. Maybe Ben Cohen has it ?

Anyway, inside the module just do:


initial begin
  // only works in proper simulators
  assert(ArbiterPort.DATA_WIDTH == 32)
  else $fatal(2,"DATA_WIDTH must be 32bits for this module to work");
  // This should make Quartus complain (a.k.a. poor man's assertion )
  if (ArbiterPort.DATA_WIDTH != 32) Call_undef_function();
end