Partial Reconfiguration - JTAG Debug Mode

Altera_Forum · ‎04-18-2016

Hi all,

How should one instantiate a PR megafunction in order to be able to partially reconfigure the FPGA in JTAG Debug mode?

In the PR ip user guide https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_partrecon.pdf it is explained how to add PR programming files but not how to connect the IP.

JTAG mode is allowed for both internal and external host so what are the necessary steps to perform partial reconfiguration?

I hope someone who has done it before could help.

Regards,

Stef

Altera_Forum · ‎04-18-2016

Additional info:

When I try to partially reconfigure the FPGA (add PR programming file and click "Start" in Quartus Programmer) I get the following error:

12872 Partial Reconfiguration status: Cannot access the Partial Reconfiguration mega function in JTAG debug mode

Altera_Forum · ‎04-18-2016

I found the solution since it was a pretty simple problem. The nreset was always connected to '0' by default leaving the state machine always in an IDLE state.

For those who'd like to make a simple test here is the VHDL instantiation that works properly in the JTAG mode.

PR_MEGAFUNCTION : PR_ip port map(

clk => clk,

nreset => '1', -- fix at '1'

pr_start => '0',

double_pr => '0',

freeze => freeze,

status => leds,

data => (others => '0'),

data_valid => '0',

data_ready => ready

);

However, it would be nice if more experienced partial reconfiguration designers give us some useful hints in this thread.

cheers,

Stef