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Performing a signal for a certain time

Altera_Forum
Honored Contributor II
‎12-15-2014 12:54 PM
1,130 Views

Hi guys, 

How to write in VHDL code for performing out signal for a certain time ? The value of the time will be variable which depends form input value.
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Altera_Forum
Honored Contributor II
‎12-15-2014 02:30 PM
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Use a counter.

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