Phase lock loop

[Altera_Forum]

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???

[Altera_Forum]

Hi i am implementing phase lock loop in altera cyclone II. I wrote my code in vhdl. My input is 60 Hz analog signal, here are my questions, 

 1. How i should convert 60 Hz analog to digital signal using vhdl coding?  2. I implemented phase detected and its perfectly finding the phase error and loop filter is also working well finding the measure of phase error.  The above two i have implemented in two process. Now comes the difficult situation, when i am using the clock in third process which is digital controlled oscillator, it says that " couldn't implement registers for assignments on this clock edge " . How i should solve this error ???  i tested phase detected and loop filter using 60 Hz digital signal. I want to know converting digital to analog using vhdl coding?

[Altera_Forum]

1) you can't do that with just VHDL. You need an external ADC chip. 

2) it depends on how you coded your process. Having both rising and falling edges conditions in the same process can produce that error.