Pin seen as a clock in TimeQuest but is not a Clock

[Altera_Forum]

I have been getting an error Node: GND was determined to be a clock but was found without an associated clock assignment.  

 The pin has nothing to do with a clock, and I do not see how TimeQuest figured it to be a clock. Is there a way to force TimeQuest to not think it is a clock?   I have tried to inject a frequency that would benefit my design, but I kept getting setup and hold violations.   Any and all help is welcome. Let me know if you need more details.

[Altera_Forum]

Firstly Do you have your project sdc? Secondly what is pin GND doing, is't connected to any process edge trigger statement. 

 Otherwise it is quite odd that you get this message (I remember signaltap clock may give rise to such warning, sort of bug)

[Altera_Forum]

By Project SDC do you refer to my TimQuest SDC or something else?  

 My GND is not doing anything except feeding into combinational logic blocks an externally forced '0'. Basically I designed a delay loop using XORs. A counter feeds wave into the logic blocks, that way it can be delayed by a certain amount. (Please do not question why I did this, and no I don't need suggestions to make this different).   Side note, if I take away GND as a pin, and make it a signal that is forced to '0', than TQ says that another pin (completely seperate from what GND interacts with) is said to be a clock but isn't.   Here are snap shots of source and destinations of GND:  imgur.com/eIaL9 imgur.com/bPWO4

[Altera_Forum]

project sdc is TQ sdc and I will assume you have it and your design is using it. 

I can't think why TQ is behaving like that. I imagine it will say that if any signal is used as edge trigger on registers or possibly connected to a clock network. I take it that you haven't connected GND to a clock pin or you haven't let quartus fitter do that.  It will help to see your design schematic or code.

[Altera_Forum]

I'll warn you, its not pretty :) The large amounts of muxs is a 32:1 mux that is constructed of 2:1 muxs. Its so that I can choose a specific point of my delayed wave to be outputed. What I have constructed is a Single-Phase Heterogeneous DPWM. Delay-line and multiplexer type DPWM is similar to what I have created if that also helps.  

 1: imgur.com/rK48A 2: imgur.com/mqOm9 3: imgur.com/qsrjg

[Altera_Forum]

Unfortunately your links are dead. Probably you need more posts to get them alive.

[Altera_Forum]

Lets try again: 

 1) http://imgur.com/rk48a 2) http://imgur.com/mqom9 3) http://imgur.com/qsrjg

[Altera_Forum]

Well interesting design. The only thing I notice is GND has widespread connections which either fooled TQ or fell with its definition of clock or it decided to connect to global clock network.  

A work around would be do declare it as clock then set it to very low frequency - just a thought.  However I am a bit lost now because I know TQ reports violations on setup/hold on clocked registers and only on paths between clocked registers. So far I didn't see those paths. Nevertheless you should get delay information.

[Altera_Forum]

When I set GND as a clock I get setup and hold violations. I set it to a very low frequency and only pulse for roughly 2ns. My master clock runs at 50MHz.

[Altera_Forum]

It is very strange indeed that you get violations when there no registers to be violated. In the classic timing analyser there was "not clock" option but haven't seen it in TQ. You can now try either set frequency to zero for GND or set false path.

[Altera_Forum]

I have been trying to find a way to do the false path option. That would seem like a better way to fix this error. How would I go about doing this?

[Altera_Forum]

I31out0 is your clock and is a feedback output from comb logic involving GND. I think this has fooled TQ.

[Altera_Forum]

Thus you have actually a timing path (from Q output of your registers through the xor logic and back into register clock port. I think it is more appropriate to declare generated clock as you are dealing with gated clock. The best way to see examples at TQ resource centre.

[Altera_Forum]

An alternative safer way is to clock both registers on clk then use I31_out0 as clock enable

[Altera_Forum]

Thanks, I'll look into that. I have never dealt with generated clocks before so I guess I have a lot of research to do.

[Altera_Forum]

Notice that even with generated clock you are likely to have serious timing violations due to the very long comb path. As I said a clock enable approach is best in your design if it is ok functionally and even then you may have to face the challenge e.g by adding more pipeline registers.

[Altera_Forum]

What is a clock enable approach?

[Altera_Forum]

Connect master clock to all registers. connect I31_out0 to the enable port of those registers which you have clocked by I31_out0. That way the enable is synchronised to master clock. The only concern then is that enable may be very much delayed. Try it first and let us see.